單邊加熱法應用於三維積體電路晶片對基板接合與低溫非對稱混合接合研究

Abstract

因應目前晶片微縮的必要性，三維積體電路應用於先進封裝製程日趨重要，其中晶片等級的接合具有最佳良率但是產量極低，晶圓等級的接合雖有著高產量，但伴隨著較低整體良率，而晶片對晶圓的接合因為已知優良晶片的選用，成為可兼顧良率以及產量的製程方法，為目前商業化量產的主流。 傳統熱壓接合需要在上下基板皆加上熱源，即使是在低溫的銅-銦接合，大氣條件下，攝氏一百七十度的溫度仍會造成下方的銅氧化，導致後續接合強度以及電性的劣化，為了改善此狀況，本論文使用單邊加熱的方法，只在上方施加熱源，以避免下方之基板受到持續的加熱而發生不良影響。 本研究測試結果顯示銅銦金屬單邊加熱比起傳統雙邊加熱有較佳的接合以及電性結果，經過濕度及溫度循環測試後仍可保持優良的電性特性，證明此方法可應用於晶片對晶圓接合製程，並提供良好的接合品質和可靠度；在高分子(SU-8)晶片對氧化矽晶圓接合部分，由於下方氧化物沒有因反覆加熱的劣化問題，本研究同時完成單邊及雙邊加熱方法下最佳的接合條件，以及兩段式接合設計，透過晶片接合以及後續的晶圓等級加溫加壓，可望應用於晶片對晶圓等級的混和接合製程。 另一方面，本研究發展低溫的混合接合製程，使用銅鎳銦-鎳銅金屬線接合與SU-8高分子材料作為間隙填充及機械強度支撐，兩者在170 oC，9000 以及三十分鐘的接合條件下同時達到混合接合的條件，透過不同的厚度比例設計，得到當高分子及金屬厚度比例為0.9:1時，會有最佳的接合結果。

In response to necessity of chip size scaling down, 3D integration applied in advanced packaging procedures becomes more important. The chip level and wafer level bonding are competitive in yield and throughput separately. Because of the usage of known good die, chip-to-wafer packaging can solve the trade-off problem and become the mainstream. In conventional thermo-compression bonding, we supply heat source on both top and bottom chips. Even in low temperature Cu-In bonding, the bonding temperature at 170 ⁰C on bottom substrate induces copper oxidize and degrade the bonding quality and electrical property. In order to improve the issues, this study chooses single side heated method. We supply heat only on top chip to avoid the degradation of bottom substrate because of lasting heated. This study shows that Cu-In single side heated bonding has better bonding quality and electrical characteristics than conventional double side heated method. Interconnects still maintain good electrical properties after reliability test such as TCT and unbiased HAST and prove that the single side heated provides good bonding quality and reliability for chip-to-wafer bonding process. In addition, we find out the optimized bonding condition for single and double side heated in SU-8 to oxide bonding and the two-step bonding method. We expect that through the chip bonding and following wafer bonding can be applied in hybrid bonding in chip-to-wafer stacking. On the other side, the low temperature hybrid bonding with Cu/Ni/In-Ni/Cu metal line and SU-8 to oxide bonding underfill is demoed. The polymer to metal thickness ratio of 0.9:1 has better bonding result in this research.