三維積體電路之暫時性接合其高分子形貌分析與超薄緩衝層應用於非對稱低溫接合結構

Abstract

暫時性接合和永久性接合是三維積體電路中重要的兩大接合技術。暫時性接合技術廣泛的應用於晶片研磨、超薄晶片處理及背面晶元的製程，而表面的平坦度在暫時性接合中扮演著相當重要的角色。在本研究中，我們將可被光蝕刻的高分子材料及可被當成黏著層的高分子材料進行暫時性接合，並應用在多種表面起伏的晶片。當晶片表面起伏低於5微米時，藉由適當的參數調變能夠得到相當好的接合結果及接合強度。 另一方面，本研究結合超薄緩衝層(10 nm)技術於銅銦錫接合中，藉由超薄緩衝層的技術，成功克服了結構的微縮極限及熱成本過高的問題。結合金屬鎳作為緩衝層之銅銦錫接合結構在低溫製程(150 °C)中成功接合，並針對此結構我們進行材料分析及機械強度的測試，在分析中顯示出良好的接合品質及接合強度。此外，在電性及可靠度分析中，呈現出良好的電性特性及在濕度測試環境和熱應力測試中有好的穩定性。基於良好的接合結果、電性特性及可靠度，超薄緩衝層技術於銅銦錫接合具備應用於三維積體電路中的潛力。

Temporary bonding and permanent bonding are two important techniques for bonding technology in 3D integration. Temporary bonding is a key technique in wafer grinding, ultra-thin wafer handling and backside processing. However, the morphology of device plays an important role in temporary bonding technique. In this research, the temporary bonding technique, which combines the release layer and adhesion layer, is applied on various pillar heights that are used to simulate the morphology of the devices. Good bonding result and bonding strength are achieved under 5 µm pillar height with suitable parameters. On the other hand, the combination of ultra-thin buffer layer technique with Cu-In/Sn interconnect has also been successfully investigated in this research. With the insertion of an ultra-thin buffer layer, this scheme can achieve a reduction in solder thickness, bonding temperature and bonding time. The excellent bonding quality and bonding strength are shown in the Cu-In/Sn bonded structure with Ni ultra-thin buffer layer at 150 °C for 15 min. Furthermore, good electrical characteristic is demonstrated by the modified Kelvin structure. Several reliability tests, such as thermal cycle test and un-bias highly accelerated stress test, also shows good stability in Cu-In/Sn bonded structure.