標題: 精進晶圓級封裝製程暨其材料分析
Refining The Package Processing and Material Analysis for Wafer Level Chip Scale Package
作者: 陳詠偉
簡紋濱
Chen, Yung-Wei
Jian, Wen-Bin
理學院應用科技學程
關鍵字: 晶圓級封裝;覆晶封裝;底部填充膠;環氧樹酯導電膠;WLCSP;Flipchip;Underfiller;Epoxy
公開日期: 2016
摘要: 晶圓級封裝是先進積體電路(IC)封裝方式的一種,做法是生產完整片晶 圓後進行封裝,完成後才切割製成單顆 IC,不須打線或填膠步驟,封裝之 後的晶片尺寸非常接近元件晶粒原來大小,也因此稱為晶圓級封裝(WLCSP Wafer Level Chip Scale Package),此技術為各大封裝廠研發重點項目。 本論文主要提出晶圓級封裝製程改進方法及其材料分析。論文先介紹 晶圓級封裝製程流程,接續介紹各種封裝製程的實驗方法及所使用儀器的 做動原理和製程參數,最後由實驗結果提出簡短結論。封裝材料分析改善 部分,經由電子顯微鏡(SEM)分析銀膠材料,並調整製程中印刷鋼板及印刷 刮刀的參數,來改變目前業界廣泛使用的高銀含量的導電印刷銀膠。此外, 為確保低金屬含量銀膠的印刷品質,使用白光干涉儀對不同銀含量膠印刷 後的基板測量表面高度,確認印刷後銀膠的平坦性。實驗結果證實將含銀 量由 80 %降低為 70 %的銀膠,能通過各種加速衰落及電性量測的穩定性測 試。本實驗中,為提升使封裝元件耐用程度,在完成封裝前使用業界常用 的底部填充膠,藉由噴膠儀器搭配不同黏性膠材,找出最適合的一款底部 填充膠。底部填充膠塗佈於晶片表面,有保護晶片功能,減少許多晶圓級 封裝常遭遇到的問題,譬如在晶片運送途中因碰撞而損壞問題,或是模組 打件時因受外力破壞晶片表面而造成元件異常等問題。
Wafer level package is one of the advanced integrated circuit (IC) packages.The packaging processing is carried out directly on the whole wafer after it is produced. Then, the packed wafer is cut into single ICs. Neither wire bonding nor fillers are required in the process. After being packaged and cutt, the chip size is very close to the original crystalline grain of the device. As a consequence, the packaging process is named as wafer level chip scale package(WLCSP), which is currently an important issue for the research and development of major packaging companies. Here we concentrate on refining the wafer level packaging process and packaging materials analysis. The flow of process for the wafer level packaging and the processing methods are introduced in the beginning.Our experimental methods are presented and the experimental results are summarized in short. The material analysis was carried out by using scanning electron microscope (SEM) and the sizes of silver particles were investigated. In addition, the stencil and scraper printing parameters were adjusted to improve the silver paste printing.The most importance is that the quality of silver paste printing was maintained for the paste of low concentration of silver particles. The paste printing quality was inspected by a white light interferometer. It is confirmed that the surface of the circuit board is flat and the roughness is small enough, even though the silver paste with low concentrations (such as 70%) of silver particles is used.Moreover, the using of low concentration silver paste passed all electrical measurements and reliability tests as well. To increase the durability of the packaging, we used under-filler with glues of different viscosity by spraying instruments for the final stage of packaging process. It is found that the under-filler coating on the surface of the wafer help to protect our ICs. The protection solves many common problems, such as damages due to the transportation of IC wafers and the surface mount device (SMT) processes.
URI: http://etd.lib.nctu.edu.tw/cdrfb3/record/nctu/#GT070352918
http://hdl.handle.net/11536/143516
顯示於類別:畢業論文