標題: Investigation of Double-Snapback Characteristic in Resistor-Triggered SCRs Stacking Structure
作者: Yen, Shiang-Shiou
Cheng, Chun-Hu
Fan, Chia-Chi
Chiu, Yu-Chien
Hsu, Hsiao-Hsuan
Lan, Yu-Pin
Chang, Chun-Yen
電機學院
電子工程學系及電子研究所
電子與資訊研究中心
College of Electrical and Computer Engineering
Department of Electronics Engineering and Institute of Electronics
Microelectronics and Information Systems Research Center
關鍵字: Electrostatic discharge (ESD);holding voltage;latchup immunity;power-rail clamp;silicon control rectifier (SCR);stacked SCR;transmission line pulsing (TLP);trigger voltage
公開日期: 1-Oct-2017
摘要: Achieving high latch-up immunity is critical for power-rail electrostatic discharge (ESD) clamp circuits in high-voltage (HV) integrated circuit products. To investigate how shunt resistance affects the transmission line pulsing current-voltage characteristics of resistance-triggered stacked silicon controlled rectifiers (SCRs), a lateral SCR (LSCR) and a modified LSCR were combined in several SCR stacked structures with various shunt resistances. Compared with in tradition stacked ESD cells, the snapback margin of the SCRs does not expand and can even be reduced. A high holding voltage of 33.4 V is achieved using the resistance-triggered stacked SCR technique in a 0.11 mu m32-V HV process. A trigger voltage of approximately 51 V and a failure current of 3.3 A is achieved in this experiment. According to theorem analysis based on a voltage decoupling equation, the minimum trigger voltage can probably be further reduced to 46 V by using the resistance-triggered stacked SCR technique. This paper can offer a simple guideline for designing ESD protection circuit using the resistor-triggered SCRs stacking structure.
URI: http://dx.doi.org/10.1109/TED.2017.2736511
http://hdl.handle.net/11536/143989
ISSN: 0018-9383
DOI: 10.1109/TED.2017.2736511
期刊: IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume: 64
起始頁: 4200
結束頁: 4205
Appears in Collections:Articles