Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Yang, Bo-Jun | en_US |
dc.contributor.author | Wu, Yu-Ting | en_US |
dc.contributor.author | Chiu, Yung-Yueh | en_US |
dc.contributor.author | Kuo, Tse-Mien | en_US |
dc.contributor.author | Chang, Jung-Ho | en_US |
dc.contributor.author | Wang, Pin-Yao | en_US |
dc.contributor.author | Shirota, Riichiro | en_US |
dc.date.accessioned | 2018-08-21T05:53:13Z | - |
dc.date.available | 2018-08-21T05:53:13Z | - |
dc.date.issued | 2018-02-01 | en_US |
dc.identifier.issn | 0018-9383 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/TED.2017.2784419 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/144404 | - |
dc.description.abstract | A method to analyze the kinetics of the charge accumulation in the tunnel oxide by the nand flash memory program and erase (P/E) cycling is proposed. Both electron trapping and detrapping processes are required to be considered owing to the oxide high electric field during P/E cycles. Consequently, the electron trapping in the deep trap state is concluded, whose trap energy (E-trap) is more than 3.5 eV. Furthermore, the as-grown trap state density (Ne), the trapping capture cross section (sigma), and the number of trapped positive charges can also be extracted to explain the tunneling current modulation and the V-T shift by oxide-trapped charges under the P/E stress. The trapped electrons are mainly distributed in the center of tunneloxide, and the distributed area extends as the P/E bias increases. In addition, the dependence of oxidation process is also shown. Both thermal dry and plasma oxidation have almost the same value of sigma (similar to 4x10(-17) cm(2)). However, 30% reduction of Ne is shown in plasma oxidation (similar to 1.25x10(19) cm(-3)) when compared with thermal dry oxidation (similar to 1.88 x 10(19) cm(-3)). | en_US |
dc.language.iso | en_US | en_US |
dc.subject | Flash memory reliability | en_US |
dc.subject | plasma oxidation | en_US |
dc.subject | TRAP | en_US |
dc.title | Evaluation of the Role of Deep Trap State Using Analytical Model in the Program/Erase Cycling of NAND Flash Memory and Its Process Dependence | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/TED.2017.2784419 | en_US |
dc.identifier.journal | IEEE TRANSACTIONS ON ELECTRON DEVICES | en_US |
dc.citation.volume | 65 | en_US |
dc.citation.spage | 499 | en_US |
dc.citation.epage | 506 | en_US |
dc.contributor.department | 電信工程研究所 | zh_TW |
dc.contributor.department | Institute of Communications Engineering | en_US |
dc.identifier.wosnumber | WOS:000423124500018 | en_US |
Appears in Collections: | Articles |