氧化層電場對NAND快閃記憶體保存度影響之研究

Abstract

在寫入狀態下進行保存度(retention)測試和在抹除狀態下結果是不同的，氧化層電場對於保存度測試有明顯的相依性。透過新的理論可以區分出烘烤時氧化層捕獲電荷和浮停閘極儲存電荷量的變化。更進一步可以探討在不同氧化層電場下烘烤對氧化層捕獲電荷的影響。烘烤前記憶體處在寫入狀態，電子離開陷阱應該是烘烤過程主要的現象；烘烤前記憶體處在抹除狀態，電洞離開陷阱應該是烘烤過程主要的現象。此外，烘烤前若屬抹除狀態較大的氧化層電場在烘烤時會造成較多的捕獲電洞聚集在靠近矽表面的氧化層是一個可能的模型。

Data retention characteristics of program state is different from erase state. There is evident dependence on E-field on oxide for retention test. Through new method can extract the amount of floating gate charge apart from oxide trapped charge by bake. Furthermore, we can analyze the process of oxide trapped charge shift at different E-field on oxide by bake. When memory cell is at program state before bake, electron detrap should be the main process. When memory cell is at erase state before bake, hole detrap should be the main process. Thus, as a possible model, at erase state for higher E-field on oxide more hole are trapped to oxide near silicon surface.