完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Garrido, Mario | en_US |
dc.contributor.author | Huang, Shen-Jui | en_US |
dc.contributor.author | Chen, Sau-Gee | en_US |
dc.date.accessioned | 2018-08-21T05:53:14Z | - |
dc.date.available | 2018-08-21T05:53:14Z | - |
dc.date.issued | 2018-02-01 | en_US |
dc.identifier.issn | 1549-8328 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/TCSI.2017.2722690 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/144439 | - |
dc.description.abstract | In this paper, we present new feedforward FFT hardware architectures based on rotator allocation. The rotator allocation approach consists in distributing the rotations of the FFT in such a way that the number of edges in the FFT that need rotators and the complexity of the rotators are reduced. Radix-2 and radix-2(k) feedforward architectures based on rotator allocation are presented in this paper. Experimental results show that the proposed architectures reduce the hardware cost significantly with respect to previous FFT architectures. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | Fast Fourier transform (FFT) | en_US |
dc.subject | multi-path delay commutator (MDC) | en_US |
dc.subject | pipelined architecture | en_US |
dc.subject | radix-2 | en_US |
dc.subject | radix-2(k) | en_US |
dc.title | Feedforward FFT Hardware Architectures Based on Rotator Allocation | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/TCSI.2017.2722690 | en_US |
dc.identifier.journal | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | en_US |
dc.citation.volume | 65 | en_US |
dc.citation.spage | 581 | en_US |
dc.citation.epage | 592 | en_US |
dc.contributor.department | 電機工程學系 | zh_TW |
dc.contributor.department | Department of Electrical and Computer Engineering | en_US |
dc.identifier.wosnumber | WOS:000423559000014 | en_US |
顯示於類別: | 期刊論文 |