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dc.contributor.authorLee, Wei-Lien_US
dc.contributor.authorZhang, Jun-Linen_US
dc.contributor.authorTsai, Ming-Lien_US
dc.contributor.authorWang, Shin-Yuanen_US
dc.contributor.authorLuo, Guang-Lien_US
dc.contributor.authorChien, Chao-Hsinen_US
dc.date.accessioned2018-08-21T05:53:19Z-
dc.date.available2018-08-21T05:53:19Z-
dc.date.issued2018-01-01en_US
dc.identifier.issn2162-8769en_US
dc.identifier.urihttp://dx.doi.org/10.1149/2.0181802jssen_US
dc.identifier.urihttp://hdl.handle.net/11536/144536-
dc.description.abstractIn this study, we employed low-pressure oxidation (LPO) to achieve a high-quality dielectric gate stack on high-Ge-content (HGC) Si0.16Ge0.84. According to X-ray photoelectron spectroscopy depth-profiling results, lowering the oxidation pressure can drive out-diffusion of Si atoms from the HGC SiGe surface, resulting in the suppression of GeOx formation. A nearly GeOx-free interfacial layer detected at an O-2 pressure of 0.01 torr at 600 degrees C was used. Consequently, the formation of stable SiOx resulted in the improvement of D-it and gate leakage current, which in accumulation (V-FB-1V) was also considerably reduced with an equivalent oxide thickness of 1.5 nm. Finally, by applying the LPO process and optimized process conditions, the interface trap density (D-it) was reduced to 2 x 10(12) eV(-1) cm(-2). (C) 2018 The Electrochemical Society.en_US
dc.language.isoen_USen_US
dc.titleStudy of High-Ge-Content Si0.16Ge0.84 Gate Stack by Low Pressure Oxidationen_US
dc.typeArticleen_US
dc.identifier.doi10.1149/2.0181802jssen_US
dc.identifier.journalECS JOURNAL OF SOLID STATE SCIENCE AND TECHNOLOGYen_US
dc.citation.volume7en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000425215200009en_US
Appears in Collections:Articles