Title: An I/O Scheduling Strategy for Embedded Flash Storage Devices With Mapping Cache
Authors: Ji, Cheng
Chang, Li-Pin
Wu, Chao
Shi, Liang
Xue, Chun Jason
資訊工程學系
Department of Computer Science
Keywords: Embedded system;flash memory performance;I/O scheduling;mapping cache
Issue Date: 1-Apr-2018
Abstract: NAND flash memory has been the default storage component in embedded systems. One of the key technologies for flash management is the address mapping scheme between logical addresses and physical addresses, which deals with the inability of in-place-updating in flash memory. Demand-based page-level mapping cache is often applied to match the cache size constraint and performance requirement of embedded storage systems. However, recent studies showed that the management overhead of mapping cache schemes is sensitive to the host I/O patterns, especially when the mapping cache is small. This paper presents a novel I/O scheduling scheme, called MAP+, to alleviate this problem. The proposed scheduling approach reorders I/O requests for performance improvement from two angles. Prioritizing the requests that will hit in the mapping cache, and grouping requests with related logical addresses into large batches. Batches of requests are reordered to further optimize request waiting time. Experimental results show that MAP+ improved upon traditional I/O schedulers by 48% and 18% in terms of read and write latencies, respectively.
URI: http://dx.doi.org/10.1109/TCAD.2017.2729405
http://hdl.handle.net/11536/144701
ISSN: 0278-0070
DOI: 10.1109/TCAD.2017.2729405
Journal: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
Volume: 37
Begin Page: 756
End Page: 769
Appears in Collections:Articles