完整後設資料紀錄
DC 欄位語言
dc.contributor.authorTang, Ya-Shengen_US
dc.contributor.authorChen, Hsiu-Chien_US
dc.contributor.authorKho, Yi-Tungen_US
dc.contributor.authorHsieh, Yu-Shengen_US
dc.contributor.authorChang, Yao-Jenen_US
dc.contributor.authorChen, Kuan-Nengen_US
dc.date.accessioned2018-08-21T05:53:52Z-
dc.date.available2018-08-21T05:53:52Z-
dc.date.issued2018-07-01en_US
dc.identifier.issn2156-3950en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TCPMT.2018.2838047en_US
dc.identifier.urihttp://hdl.handle.net/11536/145269-
dc.description.abstractUltrathin buffer layers (UBLs) with varied thickness ranging from 10 to 100 nm and different materials were used in Cu/Sn eutectic bonding. A Cu/Sn film thinner than 2 mu m could fully react and became stiff and rough Cu-Sn intermetallic compound layer, which leads to failure bonding. Four kinds of semiconductor compatible materials including Ti, Pd, Co, and Ni were inserted between Cu/Sn to delay interdiffusion prior to eutectic bonding. In addition to symmetric Cu/Sn bonding with UBL, asymmetric Cu/Sn-Cu bonding scheme with 50-nm Ni UBL was demonstrated. With good mechanical properties, bonding quality, and electrical characteristics, the application of submicrometer Cu/Sn wafer-level bonding by assistance of buffering layer gives a promising and flexible platform for future 3-D integration applications.en_US
dc.language.isoen_USen_US
dc.subject3-D integrationen_US
dc.subjecteutectic bondingen_US
dc.subjectultrathin buffer layer (UBL)en_US
dc.titleInvestigation and Optimization of Ultrathin Buffer Layers Used in Cu/Sn Eutectic Bondingen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TCPMT.2018.2838047en_US
dc.identifier.journalIEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGYen_US
dc.citation.volume8en_US
dc.citation.spage1225en_US
dc.citation.epage1230en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000438909700012en_US
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