完整後設資料紀錄
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dc.contributor.authorZhong, Chia-Wenen_US
dc.contributor.authorLin, Horng-Chihen_US
dc.contributor.authorTsai, Jung-Rueyen_US
dc.contributor.authorLiu, Kou-Chenen_US
dc.contributor.authorHuang, Tiao-Yuanen_US
dc.date.accessioned2018-08-21T05:53:54Z-
dc.date.available2018-08-21T05:53:54Z-
dc.date.issued2016-04-01en_US
dc.identifier.issn0021-4922en_US
dc.identifier.urihttp://dx.doi.org/10.7567/JJAP.55.04EG02en_US
dc.identifier.urihttp://hdl.handle.net/11536/145306-
dc.description.abstractIn this work, we study the impact of gate dielectrics on the characteristics of bottom-gated tin-oxide thin-film transistors annealed in an oxygen ambience at 300 degrees C for various periods. SiO2, HfO2, and Al2O3 are employed as the gate dielectric in the test devices. The results show that the devices will start exhibiting p-type conduction behavior as the annealing reaches a specific time period which is closely related to the underlying gate dielectric, and the device characteristics can be improved as the annealing proceeds further. Nonetheless, a prolonged annealing may cause degradation of the devices. High hole mobility (3.33 cm(2)V(-1)s(-1)), low threshold voltage (1.95 V), and excellent I-on/I-off ratio (similar to 10(4)) are achieved on SnO TFTs with a SiO2 gate dielectric after an annealing of 30 min. (C) 2016 The Japan Society of Applied Physicsen_US
dc.language.isoen_USen_US
dc.titleImpact of gate dielectrics and oxygen annealing on tin-oxide thin-film transistorsen_US
dc.typeArticleen_US
dc.identifier.doi10.7567/JJAP.55.04EG02en_US
dc.identifier.journalJAPANESE JOURNAL OF APPLIED PHYSICSen_US
dc.citation.volume55en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000373929400082en_US
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