標題: | A 16-Gb/s 14.7-mW Tri-Band Cognitive Serial Link Transmitter With Forwarded Clock to Enable PAM-16/256-QAM and Channel Response Detection |
作者: | Du, Yuan Cho, Wei-Han Huang, Po-Tsang Li, Yilei Wong, Chien-Heng Du, Jieqiong Kim, Yanghyo Hu, Boyu Du, Li Liu, Chunchen Lee, Sheau Jiung Chang, Mau-Chung Frank 交大名義發表 National Chiao Tung University |
關鍵字: | Cognitive;continuous-time linear equalization (CTLE);decision feedback equalization (DFE);digital modulation;energy efficiency;feedforward equalization (FFE);forwarded clock;Inter-Symbol Interference (ISI);memory interface;uW/Gb/s/dB;multiband signaling;multidrop bus (MDB);multilevel signaling;nonreturn to zero (NRZ);pulse-amplitude modulation (PAM);quadrature amplitude modulation (QAM);serial link;source synchronous;transmitter (TX);wireline |
公開日期: | 1-四月-2017 |
摘要: | A cognitive tri-band transmitter (TX) with a forwarded clock using multiband signaling and high-order digital signal modulations is presented for serial link applications. The TX features learning an arbitrary channel response by sending a sweep of continuous wave, detecting power level at the receiver side, and then adapting modulation scheme, data bandwidth, and carrier frequencies accordingly based on detected channel information. The supported modulation scheme ranges from nonreturn to zero/Quadrature phase shift keying (QPSK) to Pulse-amplitude modulation (PAM) 16/256-Quadrature amplitude modulation(QAM). The proposed highly reconfigurable TX is capable of dealing with low-cost serial channels, such as low-cost connectors, cables, or multidrop buses with deep and narrow notches in the frequency domain (e.g., a 40-dB loss at notches). The adaptive multiband scheme mitigates equalization requirements and enhances the energy efficiency by avoiding frequency notches and utilizing the maximum available signal-to-noise ratio and channel bandwidth. The implemented TX prototype consumes a 14.7-mW power and occupies 0.016 mm(2) in a 28-nm CMOS. It achieves a maximum data rate of 16 Gb/s with forwarded clock through one differential pair and the most energy efficient figure of merit of 20.4 mu W/Gb/s/dB, which is calculated based on power consumption of transmitting per gigabits per second data and simultaneously overcoming per decibel worst case channel loss within the Nyquist frequency. |
URI: | http://dx.doi.org/10.1109/JSSC.2016.2628049 http://hdl.handle.net/11536/145343 |
ISSN: | 0018-9200 |
DOI: | 10.1109/JSSC.2016.2628049 |
期刊: | IEEE JOURNAL OF SOLID-STATE CIRCUITS |
Volume: | 52 |
起始頁: | 1111 |
結束頁: | 1122 |
顯示於類別: | 期刊論文 |