應用於序列傳輸系統之10-Gbps離散時間適應性等化器

Abstract

隨著積體電路製程技術的進步，晶片的操作速度變得越來越快，晶片間傳遞資料的高頻寬輸出入介面愈來愈重要。各種高速序列傳輸技術廣泛的使用在許多高效能的電子產品中。為了讓訊號經過傳輸通道衰減後可以維持一定的品質，等化器在高速序列傳輸系統中扮演了重要的角色。而由於通道的特性會因為環境而改變，適應性等化器較適合於長時間的使用。 在本論文中，我們提出了一個操作在10 Gbps 2-tap的離散時間適應性決策回授等化器。在等化器系統的前端，我們設計了一個可變增益的放大器，來調整輸入訊號的振幅到下一級電路接受的範圍。另外，我們設計了一個高速、電流模式的加法器，用來消除post-cursor ISI。接著，我們提出一個叫跳躍式係數更新的方案，還有一個混合訊號的積分器，來實現係數更新的機制。跳躍式係數更新方案可以藉由降低係數更新的速度，來減少功率的消耗。混合訊號積分器是由一個四位元的上數下數計數器和一個電荷幫浦組成，用來獲取更好的輸出表現和較小的面積。我們使用了延遲sign-sign LMS演算法來做係數的收斂。提出的等化器是用65奈米互補式金氧半導體製程來設計。模擬結果位於等化器輸出的信號眼圖可以開至正負200 mV，而緩衝器的輸出端可以將信號眼圖張開到規格所定的正負300 mV。在等化器輸出的峰對峰值抖動大約31ps。而係數的收斂時間約為20000個位元時間。電路總面積為510 × 510 μm2，而核心電路面積是115 × 95 μm2。在1.2V的操作電壓下，電路總功率為40.63 mW，其中等化器系統佔了11.18 mW。

With the advance of integrated circuits (IC) fabrication technology, the operation speed of chips is becoming faster and faster. High-bandwidth I/Os have found a great demand for transferring data between chips. Many high-speed serial link transmission technologies are developed and are widely used for high performance modern electronic products. In order to maintain the signal quality that will be attenuated by communication channel, the equalizer becomes an important component in the high-speed serial link system. Since the characteristics of channel may vary due to the environment, adaptive equalizer is much preferable for long-time usage. In this thesis, we propose a 2-tap discrete-time adaptive decision-feedback equalizer that operates at 10 Gbps. We design a variable gain amplifier in the front of the proposed equalizer system to adjust the swing of input signal in the range for the following stage. A high-speed current-mode summer is designed to cancel the post-cursor ISI. A coefficient updating scheme called hopping and a mixed-signal integrator are presented to realize the mechanism of coefficients adaptation. The hopping update scheme can reduce the power consumption by slowing down the operation speed in the coefficients adaptation. The mixed-signal integrator consists of a 4-bit up/down counter and a charge pump to acquire a good performance and small area. We use the delayed sign-sign LMS algorithm to do the convergence of coefficients. The proposed equalizer is designed in a 65-nm CMOS technology. The simulation result shows that the data eye in the output of equalizer is about ±200 mVpp, and the data eye in the output of buffer stage can reach ±300 mVpp that meets our specification. The peak-to-peak jitter at the equalizer output is about 31ps. The convergence time of coefficients is about 20000 bits time. Total area of our proposed equalizer including pads is 510 × 510 μm2 while the core area is 115 × 95 μm2. The total power consumption is 40.63 mW while the equalizer system consumes 11.18 mW under 1.2V power supply.