用於8Gbps串列收發機之低功耗技術

Abstract

端運算及網路的發展使得高速傳輸的需求與日俱增。近年來有線傳輸系統已發展至每秒數億個位元的傳輸速度，由於在有線平行傳輸系統中，高速訊號之間會有互相干擾的行為，且需要較大的面積，因此，為了降低干擾及介面尺寸，現今都採用串列傳輸介面。此外，有限的通道頻寬將使資料在傳送時產生符際干擾(Inter Symbol Interference，簡稱ISI)，嚴重的話將導致資料接受錯誤。因此序列傳輸系統中的平行序列轉換器(Serializer)、序列平行轉換器(Deserializer)以及等化器(Equalizer)皆扮演極重要的角色。 本論文提出一個操作於8Gbps的四對一轉態偵測多工器以及一個搭配等化器之一對四解多工器。其中四對一多工器為轉態偵測架構，透過轉態偵測電路來判定輸出訊號是否有轉態之必要性，並依據其必要性來進行資料轉態與否之動作，因為傳統架構不論資料是否相同皆會一直運作，所以本論文期望透過減少非必要資料轉態的次數來達到低功耗的需求，且同時可適用於高速之應用，在此以數位邏輯的方式實現之。另外，解多工器則是採用多相位時脈訊號的型式，其時脈訊號來自四級的注入鎖定環狀振盪器。等化器的部分則包含類比等化器以及採用Sign-Sign LMS演算法之軟式決策回授等化器，期望達到適應性調整係數，並解決通道頻寬不足所造成的符際干擾。 本設計之雛型晶片採用UMC 55nm 互補式金氧半導體製程技術，操作於1V的供應電壓。多工器的總面積為720*750μm2，核心電路面積則為77*81μm2，其模擬時之功率消耗為6.3mW，輸出緩衝器為15.8mW，量測時使用1.2V進行量測，其核心電路功耗為10.3mW，輸出緩衝器則為24mW。解多工器與等化器的總面積為950*1500μm2，模擬時之功率消耗分別為7.9mW以及35.8mW。

Cloud computing and internet technology are developing tremendously in these years. The demands of high speed and enormous data transmission increase drastically. Recently, the speed of wireline data transmission has reached to gigabits per second. To circumvent cross-talk in parallel transmission system and reduce form factor, serial link data transmission has become main stream for high speed interface. And the issue for high speed serial link is the limited bandwidth which induces ISI. It may degrade receiver’s BER performance. Thus serializer, deserializer, and equalizer play an important role in serial link data transmission. In this thesis, an 8Gbps 4:1 transition-aware multiplexer (MUX) is proposed. Power consumption can be reduced by reducing the triggling rate of the MUX. In the meantime, it can also be applied to high speed applications. An 8Gbps 1:4 demultiplexer (DEMUX) with an equalizer is also proposed and realized in this thesis. DEMUX is implemented with multi-phase clock signals, which are generated by a 4-stage injection-locked ring oscillator. The equalizer is composed of an analog equalizer (AEQ) and a soft-decision feedback equalizer (Soft-Decision DFE) with Sign-Sign LMS algorithm. It will adjust the coefficients in the equalizer via the algorithm, and eliminate the ISI generated by channel. The experimental prototypes are implemented with UMC 55nm standard CMOS process. The whole chip area of MUX is 720*750μm2 and the core area is 77*81μm2. The power consumption of core circuit and output buffer are 6.3mW and 15.8mW respectively. Measured from a 1.2V supply voltage, the power consumption for core circuit and output buffer are 10.3mW and 24mW respectively. The whole chip area of DEMUX and equalizer is 950*1500μm2 and the power consumption in simulation are 7.9mW and 35.8mW respectively.