奈米CMOS之高性能類比數位混合信號關鍵電路設計技術---子計畫六：用於高密度高速連結系統之矽光電積體電路

Abstract

多核心運算技術為未來高性能處理器之主流技術，其可提升整體運算效能、增加 硬體使用效率、降低功耗、同時提高製程之良率。然而在此高資料密度之計算平台，資 料交換之通道頻寬將成為系統之瓶頸。在系統晶片整合上，傳統之電信號聯結通道將遭 遇嚴重之信號偶合、符元干擾、以及電磁輻射干擾等問題；此外，其在同步數位系統中 所衍生之時脈抖動與傳遞延遲，亦將增加系統設計之複雜度。因此，光通道連結系統在 奈米電路時代已被視為極具潛力之技術，以克服上述之困難，進而達成有效的封裝級系 統整合。 本計畫預計以 3 年時間研發矽光電積體電路，設計內容包含矽光檢測器電路、發 射機電路、與接收機電路開發，以期實現高密度、多通道 (> 4)、高速 (>10 Gbps/channel) 光連結系統，進而應用於未來兆位元 (Tera-bits)運算平台，同時達到低成本、極高速、 與高整合度之目標。為達此一設計目標，其主要需克服之設計困難包含:矽光檢測器之 頻寬與功率響應及增益問題，雷射二極體 （VCSEL）之速度極限，系統晶片載具內光波 導之頻寬限制，以及多通道、高速之混合信號積體電路在低功率目標上設計之挑戰。 據此，本計畫第一年之研究重點將包含開發標準 CMOS 製程之極高速 (>10 Gbps) 光檢測器，同時配合此檢測器實現高感度之單晶片光接收機電路，內含轉阻放大器、可 調增益放大器、等化器、與時脈資料回復電路等。第二年之研究內容將以發射端電路之 開發為主，內含時脈取樣與波形回復電路，工作周期校正電路，雷射二極體驅動電路， 主動匹配網路，與調變電路設計等。第三年則將延續前二年之研究成果，同時藉由多位 準調變技術以進一步提升資料之傳輸速率，並開發多通道傳輸技術，以期實現高速、高 密度、低錯誤率、與低功率消耗之目標。 本計畫中傳輸接收端之各子電路模組將經由仔細之設計、模擬、佈局、檢測、與 驗證。電路之製造將委由國科會晶片設計製造中心統籌下線。除了電路技術之研究外， 本計劃亦將發展高速傳輸之晶片內傳輸錯誤率估計技術，以減低量測上之困難度。預 料本計畫之研究成果對於國內傳輸介面電路技術之發展，將可提供直接之助益。

Multicore microprocessors have become the main stream for high performance computing system in the future. It can boost the operating speed, enhance the hardware efficiency, reduce power dissipation, and improve the yield rate for manufacture. In such a data intensive computing plate form, the data bandwidth for system integration has become the performance bottleneck. Conventional electrical interconnects in such a high speed, multi-channels scenario will suffer from severe cross talk, inter-symbol interference, and electro-magnetic interference problems. Besides, the worsened clock jitter and timing skew in synchronous digital system demand more and more sophisticated design to overcome these problems. As a consequence, optical links for system chips integration have been considered as a potential candidate to overcome the design challenges mentioned above. The objective goal of this project is to deliver silicon photonics, including photo detectors and optical transceivers, for high density, multi-lane ( > 4 channels), and high speed (> 10 Gbps/channel) optical interconnects to be applied in the future Tera-bits computing plate form. To achieve the design goals of low cost, ultra high speed, and high integration level, the major design issues include the low bandwidth and responsivity of Silicon-photo receiver, the speed limitation of VCSEL diode, and bandwidth limitation of optical waveguide in the carrier of system chips, and other challenges coming from multi-lane, high speed, and low power mixed-signal integrated circuit design. Based on the strategic plan, in the first year, the major working tasks are focused on the developing of ultra high speed (>10 Gbps) photo detectors in generic CMOS technology. Meanwhile, single chip optical receivers incorporating the proposed photo detector, transimpedance amplifier, automatic gain control circuits, equalizer, and clock and data recovery circuits will be developed. In the second year, the research work will target on the transmitter design, including data retiming, waveform shaping, duty cycle correction, laser driver, active termination network, and modulator design. Based on the research accomplishments of the previous two years, the major works in the third year are to develop multi-channels technologies and boost the data rate by employing pulse amplitude modulation techniques to full-fill high speed, high densitity, low bit error rate, and low power consumption ultimate goal. All the sub-circuits of the high speed transceiver will be carefully designed, simulated, laid-out, verified, and measured. Fabrication will be coordinated by Chip Implementation Center (CIC). In addition, we would also develop built-in test techniques of bit error rate to relax the testing complexity. Circuit techniques come out with this project would be beneficial to the developing of high speed interface circuits for domestic industry.