相容於標準金氧半技術之光接收機前端電路

Abstract

本篇論文提出兩個相容於0.18微米標準金氧半技術之高速光接收機電路。這兩個光接收機收到光訊號以後，可以將光訊號轉換成800毫伏特的電壓訊號來推動50歐姆的輸出端負載。 在第一項電路中，它將一個空間調變光感測器(Spatially Modulated Light)、一個轉阻放大器和一個後級限伏放大器整合在單一晶片裡面。利用空間調變光感測器和適應性的類比等化器(Equalizer)使本電路可以操作到每秒31.25億位元的資料速度。整顆晶片耗功175毫瓦。晶片面積是0.7平方毫米。 另外一項電路，它也整合了一個光感測器、一個轉阻放大器和一個後級限伏放大器在單一晶片裡面。在不改變製程技術的情況下，我們提出一個新型的PIN光感測器。因為有它，所以不需要等化器就可以操作到每秒25億位元的資料速度。整顆晶片耗功138毫瓦。晶片面積是0.53平方毫米。

The thesis presents two solutions of the monolithically-integrated high-speed optical receivers in standard 180-nm CMOS technology. The optical receivers are capable of delivering 800 mVpp to 50 ohms output load after optical to electrical conversion. For the first one, it integrates a spatially modulated light (SML) detector, a transimpedance amplifier (TIA), and a post limiting amplifier on a single chip. A 3.125 Gbps high speed operation is achieved by utilizing SML detector and adaptive analog equalizer (EQ). The total power dissipation is 175 mW, and the chip size is 0.7 mm2. For the other, it also includes a photodetector, a TIA, and a post limiting amplifier on a single chip. A novel PIN detector is proposed and adopted in this design without technology modification. It can operate up to 2.5 Gbps without an equalizer. The total power dissipation is 138 mW, and the chip size is 0.53 mm2