完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Yang, Keng-Hao | en_US |
dc.contributor.author | Tsai, Hsiang-Jen | en_US |
dc.contributor.author | Li, Chia-Yin | en_US |
dc.contributor.author | Jendra, Paul | en_US |
dc.contributor.author | Chang, Meng-Fan | en_US |
dc.contributor.author | Chen, Tien-Fu | en_US |
dc.date.accessioned | 2018-08-21T05:53:55Z | - |
dc.date.available | 2018-08-21T05:53:55Z | - |
dc.date.issued | 2017-04-01 | en_US |
dc.identifier.issn | 1549-8328 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/TCSI.2016.2620520 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/145347 | - |
dc.description.abstract | As 2.5D/3D die stacking technology emerges, stacked dynamic random access memory (DRAM) has been proposed as a cache due to its large capacity in order to bridge the latency gap between off-chip memory and SRAM caches. The main problems in utilizing a DRAM cache are the high tag storage overhead and the high lookup latency. To address these, we propose tags-in-eDRAM (embedded DRAM) due to its higher density and lower latency. This paper presents an eTag DRAM cache architecture that is composed of a novel tag-comparison-inmemory scheme to achieve direct data access. It eliminates access latency and comparison power by pushing tag-comparison into the sense amplifier. Furthermore, we propose a Merged Tag to enhance the eTag DRAM cache by comparing last-level cache tags and DRAM cache tags in parallel. Simulation results show that the eTag DRAM cache improves energy efficiency by 15.4% and 33.9% in 4-core and 8-core workloads, respectively. Additionally, the Merged Tag achieves 32.1% and 48.7% energy efficiency improvements in 4-core and 8-core workloads, respectively. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | Cache memory | en_US |
dc.subject | DRAM chips | en_US |
dc.subject | memory architecture | en_US |
dc.subject | memory management | en_US |
dc.subject | system-on-chip | en_US |
dc.title | eTag: Tag-Comparison in Memory to Achieve Direct Data Access based on eDRAM to Improve Energy Efficiency of DRAM Cache | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/TCSI.2016.2620520 | en_US |
dc.identifier.journal | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | en_US |
dc.citation.volume | 64 | en_US |
dc.citation.spage | 858 | en_US |
dc.citation.epage | 868 | en_US |
dc.contributor.department | 資訊工程學系 | zh_TW |
dc.contributor.department | Department of Computer Science | en_US |
dc.identifier.wosnumber | WOS:000399015100010 | en_US |
顯示於類別: | 期刊論文 |