完整後設資料紀錄
DC 欄位 | 值 | 語言 |
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dc.contributor.author | Zimmer, Brian | en_US |
dc.contributor.author | Lee, Yunsup | en_US |
dc.contributor.author | Puggelli, Alberto | en_US |
dc.contributor.author | Kwak, Jaehwa | en_US |
dc.contributor.author | Jevtic, Ruzica | en_US |
dc.contributor.author | Keller, Ben | en_US |
dc.contributor.author | Bailey, Steven | en_US |
dc.contributor.author | Blagojevic, Milovan | en_US |
dc.contributor.author | Chiu, Pi-Feng | en_US |
dc.contributor.author | Hanh-Phuc Le | en_US |
dc.contributor.author | Chen, Po-Hung | en_US |
dc.contributor.author | Sutardja, Nicholas | en_US |
dc.contributor.author | Avizienis, Rimas | en_US |
dc.contributor.author | Waterman, Andrew | en_US |
dc.contributor.author | Richards, Brian | en_US |
dc.contributor.author | Flatresse, Philippe | en_US |
dc.contributor.author | Alon, Elad | en_US |
dc.contributor.author | Asanovic, Krste | en_US |
dc.contributor.author | Nikolic, Borivoje | en_US |
dc.date.accessioned | 2018-08-21T05:53:58Z | - |
dc.date.available | 2018-08-21T05:53:58Z | - |
dc.date.issued | 2016-04-01 | en_US |
dc.identifier.issn | 0018-9200 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/JSSC.2016.2519386 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/145406 | - |
dc.description.abstract | This work demonstrates a RISC-V vector microprocessor implemented in 28 nm FDSOI with fully integrated simultaneous-switching switched-capacitor DC-DC (SC DC-DC) converters and adaptive clocking that generates four on-chip voltages between 0.45 and 1 V using only 1.0 V core and 1.8 V IO voltage inputs. The converters achieve high efficiency at the system level by switching simultaneously to avoid charge-sharing losses and by using an adaptive clock to maximize performance for the resulting voltage ripple. Details about the implementation of the DC-DC switches, DC-DC controller, and adaptive clock are provided, and the sources of conversion loss are analyzed based on measured results. This system pushes the capabilities of dynamic voltage scaling by enabling fast transitions (20 ns), simple packaging (no off-chip passives), low area overhead (16%), high conversion efficiency (80%-86%), and high energy efficiency (26.2 DP GFLOPS/W) for mobile devices. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | Adaptive clock | en_US |
dc.subject | DC-DC conversion | en_US |
dc.subject | dynamic voltage and frequency scaling (DVFS) | en_US |
dc.subject | fully integrated converter | en_US |
dc.subject | integrated voltage regulator | en_US |
dc.subject | noninterleaved | en_US |
dc.subject | RISC-V | en_US |
dc.subject | simultaneous-switching | en_US |
dc.subject | switched-capacitor | en_US |
dc.title | A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC-DC Converters in 28 nm FDSOI | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/JSSC.2016.2519386 | en_US |
dc.identifier.journal | IEEE JOURNAL OF SOLID-STATE CIRCUITS | en_US |
dc.citation.volume | 51 | en_US |
dc.citation.spage | 930 | en_US |
dc.citation.epage | 942 | en_US |
dc.contributor.department | 交大名義發表 | zh_TW |
dc.contributor.department | National Chiao Tung University | en_US |
dc.identifier.wosnumber | WOS:000374404300014 | en_US |
顯示於類別: | 期刊論文 |