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dc.contributor.authorYu, Chang-Hungen_US
dc.contributor.authorSu, Pinen_US
dc.contributor.authorChuang, Ching-Teen_US
dc.date.accessioned2018-08-21T05:53:58Z-
dc.date.available2018-08-21T05:53:58Z-
dc.date.issued2017-05-01en_US
dc.identifier.issn0018-9383en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TED.2017.2685561en_US
dc.identifier.urihttp://hdl.handle.net/11536/145420-
dc.description.abstractFor the first time, considering the architecture of monolithic 3-D integration, we evaluate and benchmark the performance of 3-D logic circuits and stability/performance of 3-D 6T SRAM cells with monolayer and few-layer transition metal dichalcogenide (TMD) devices based on ITRS 2028 (5.9 nm) technology node. The impact of random variations on the cell stability is also investigated. With the possibility of adopting monolayer or fewlayer TMDs for nFET- and pFET-tiers enabled by monolithic 3-D integration, this paper indicates that the trilayer TMD device may substantially degrade the performance of 3-D logic circuits in spite of its higher mobility. This paper also reveals that stacking the monolayer pFET-tier over the bilayer nFET-tier may provide better nominal stability and read/write performance for 6T superthreshold SRAM compared with the planar technology, whereas the optimum 3-D configuration for near-/sub-threshold operations appears to be the monolayer pFET-tier over the monolayer nFET-tier. Besides the 6T cell structure, 8T SRAM cells are also investigated with monolithic 3-D integration for near-threshold/subthreshold operation. Themonolayer nFET-tier over the bilayer pFET-tier configuration is shown to be the optimum 3-D 8T near-threshold/subthreshold cell design.en_US
dc.language.isoen_USen_US
dc.subject2-D materialsen_US
dc.subjectlogic circuitsen_US
dc.subjectmonolithic 3-D integrationen_US
dc.subjectSRAM cellsen_US
dc.subjecttransition metal dichalcogenide (TMD)en_US
dc.titlePerformance and Stability Benchmarking of Monolithic 3-D Logic Circuits and SRAM Cells With Monolayer and Few-Layer Transition Metal Dichalcogenide MOSFETsen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TED.2017.2685561en_US
dc.identifier.journalIEEE TRANSACTIONS ON ELECTRON DEVICESen_US
dc.citation.volume64en_US
dc.citation.spage2445en_US
dc.citation.epage2451en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000399935800082en_US
Appears in Collections:Articles