標題: Performance and Stability Benchmarking of Monolithic 3-D Logic Circuits and SRAM Cells With Monolayer and Few-Layer Transition Metal Dichalcogenide MOSFETs
作者: Yu, Chang-Hung
Su, Pin
Chuang, Ching-Te
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: 2-D materials;logic circuits;monolithic 3-D integration;SRAM cells;transition metal dichalcogenide (TMD)
公開日期: 1-May-2017
摘要: For the first time, considering the architecture of monolithic 3-D integration, we evaluate and benchmark the performance of 3-D logic circuits and stability/performance of 3-D 6T SRAM cells with monolayer and few-layer transition metal dichalcogenide (TMD) devices based on ITRS 2028 (5.9 nm) technology node. The impact of random variations on the cell stability is also investigated. With the possibility of adopting monolayer or fewlayer TMDs for nFET- and pFET-tiers enabled by monolithic 3-D integration, this paper indicates that the trilayer TMD device may substantially degrade the performance of 3-D logic circuits in spite of its higher mobility. This paper also reveals that stacking the monolayer pFET-tier over the bilayer nFET-tier may provide better nominal stability and read/write performance for 6T superthreshold SRAM compared with the planar technology, whereas the optimum 3-D configuration for near-/sub-threshold operations appears to be the monolayer pFET-tier over the monolayer nFET-tier. Besides the 6T cell structure, 8T SRAM cells are also investigated with monolithic 3-D integration for near-threshold/subthreshold operation. Themonolayer nFET-tier over the bilayer pFET-tier configuration is shown to be the optimum 3-D 8T near-threshold/subthreshold cell design.
URI: http://dx.doi.org/10.1109/TED.2017.2685561
http://hdl.handle.net/11536/145420
ISSN: 0018-9383
DOI: 10.1109/TED.2017.2685561
期刊: IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume: 64
起始頁: 2445
結束頁: 2451
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