完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Chang, Chih-Min | en_US |
dc.contributor.author | Wu, Jieh-Tsorng | en_US |
dc.date.accessioned | 2018-08-21T05:53:59Z | - |
dc.date.available | 2018-08-21T05:53:59Z | - |
dc.date.issued | 2017-05-01 | en_US |
dc.identifier.issn | 1549-8328 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/TCSI.2016.2634016 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/145423 | - |
dc.description.abstract | A digital class-D amplifier (CDA) converts an audio digital stream into sound directly and power-efficiently. It first encodes the pulse-code-modulated audio input into a digital pulse-width-modulated (PWM) signal. It needs a digital-to-pulse converter (DPC) to translate this digital PWM signal into a series of analog binary pulses accurately. We report a 5-3 segmented DPC that includes both a counter and a delay line for pulse width conversion. The timing skews along the delay line are detected using a zero-crossing detection scheme and corrected in the digital domain. This calibration can operate continuously in the background. A digital CDA prototype was fabricated using a 65-nm CMOS technology. It includes the aforementioned PWM modulator and DPC. It also integrated an open-loop switching driver to deliver the DPC's output to a speaker. This digital CDA consumes 875 mu W under a 1-V supply when the input is zero and no output power is transferred to the external load. It can deliver 13.3 mW to a 32 Omega resistive load in the H-bridge topology with 89% power efficiency. For a 1-kHz sine-wave input, it achieves 95 dBA dynamic range, 93.6 dBA peak SNR, 86.4 dBA peak SNDR, and 0.006% THD at -2-dBFS input level. The core area of the chip is 0.87 x 0.5 mm(2). | en_US |
dc.language.iso | en_US | en_US |
dc.subject | Class-D amplifier | en_US |
dc.subject | digital-analog conversion | en_US |
dc.subject | pulse-width modulation (PWM) | en_US |
dc.subject | switching amplifier | en_US |
dc.subject | timing-skew calibration | en_US |
dc.title | A 95-dBA DR Digital Audio Class-D Amplifier Using a Calibrated Digital-to-Pulse Converter | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/TCSI.2016.2634016 | en_US |
dc.identifier.journal | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | en_US |
dc.citation.volume | 64 | en_US |
dc.citation.spage | 1106 | en_US |
dc.citation.epage | 1117 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000399958800010 | en_US |
顯示於類別: | 期刊論文 |