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dc.contributor.authorWu, Shang-Linen_US
dc.contributor.authorLi, Kuang-Yuen_US
dc.contributor.authorHuang, Po-Tsangen_US
dc.contributor.authorHwang, Weien_US
dc.contributor.authorTu, Ming-Hsienen_US
dc.contributor.authorLung, Sheng-Chien_US
dc.contributor.authorPeng, Wei-Shengen_US
dc.contributor.authorHuang, Huan-Shunen_US
dc.contributor.authorLee, Kuen-Dien_US
dc.contributor.authorKao, Yung-Shinen_US
dc.contributor.authorChuang, Ching-Teen_US
dc.date.accessioned2018-08-21T05:54:15Z-
dc.date.available2018-08-21T05:54:15Z-
dc.date.issued2017-07-01en_US
dc.identifier.issn1549-8328en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TCSI.2017.2681738en_US
dc.identifier.urihttp://hdl.handle.net/11536/145709-
dc.description.abstractThis paper presents a 28-nm 256-kb 6T static random access memory operating down to near-threshold regime. The cell array is built on foundry 4-by-2 mini-array with split single-ended large signal sensing to enable an ultra-short local bit-line of 4-b length to improve variation tolerance and performance, and to reduce disturb while maintaining manufacturability. The design employs threshold power gating to facilitate lower NAP (Sleep) mode voltage/power and faster wake-up for the cell array, and low-swing global read bit-line (GRBL) with integrated low-swing voltage precharger to improve read performance and reduce the dynamic read power. A cell Vtrip-tracking write-assist (VTWA) lowers the selected sub-array supply to cell inverter trip voltage to enhance write-ability while providing PVT tracking capability to ensure adequate data retention margin for unselected cells in the selected sub-array. The 256-kb test chip is implemented in UMC 28-nm high-kappa metal-gate (H kappa MG) CMOS technology with macro area of 1058.22 x 374.76 mu m(2). Error-free full functionality is achieved from 0.9 down to 0.5 V (limited by read VMIN) without redundancy. The low-swing GRBL reduces dynamic power by 6.5% (8.0%) at 0.9 V (0.6 V). The VTWA improves the write VMIN by 75 mV (from 0.525 to 0.45 V). The measured maximum operation frequency is 735 MHz (20 MHz) at 0.9 V (0.5 V), TT corner, 25(omicron).en_US
dc.language.isoen_USen_US
dc.subjectLow voltageen_US
dc.subjectlow poweren_US
dc.subjectstatic random access memory (SRAM)en_US
dc.subjectwrite-assisten_US
dc.subjectpower-gatingen_US
dc.subjectnear-thresholden_US
dc.titleA 0.5-V 28-nm 256-kb Mini-Array Based 6T SRAM With Vtrip-Tracking Write-Assisten_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TCSI.2017.2681738en_US
dc.identifier.journalIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERSen_US
dc.citation.volume64en_US
dc.citation.spage1791en_US
dc.citation.epage1802en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000404294900015en_US
Appears in Collections:Articles