完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Wu, Shang-Lin | en_US |
dc.contributor.author | Li, Kuang-Yu | en_US |
dc.contributor.author | Huang, Po-Tsang | en_US |
dc.contributor.author | Hwang, Wei | en_US |
dc.contributor.author | Tu, Ming-Hsien | en_US |
dc.contributor.author | Lung, Sheng-Chi | en_US |
dc.contributor.author | Peng, Wei-Sheng | en_US |
dc.contributor.author | Huang, Huan-Shun | en_US |
dc.contributor.author | Lee, Kuen-Di | en_US |
dc.contributor.author | Kao, Yung-Shin | en_US |
dc.contributor.author | Chuang, Ching-Te | en_US |
dc.date.accessioned | 2018-08-21T05:54:15Z | - |
dc.date.available | 2018-08-21T05:54:15Z | - |
dc.date.issued | 2017-07-01 | en_US |
dc.identifier.issn | 1549-8328 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/TCSI.2017.2681738 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/145709 | - |
dc.description.abstract | This paper presents a 28-nm 256-kb 6T static random access memory operating down to near-threshold regime. The cell array is built on foundry 4-by-2 mini-array with split single-ended large signal sensing to enable an ultra-short local bit-line of 4-b length to improve variation tolerance and performance, and to reduce disturb while maintaining manufacturability. The design employs threshold power gating to facilitate lower NAP (Sleep) mode voltage/power and faster wake-up for the cell array, and low-swing global read bit-line (GRBL) with integrated low-swing voltage precharger to improve read performance and reduce the dynamic read power. A cell Vtrip-tracking write-assist (VTWA) lowers the selected sub-array supply to cell inverter trip voltage to enhance write-ability while providing PVT tracking capability to ensure adequate data retention margin for unselected cells in the selected sub-array. The 256-kb test chip is implemented in UMC 28-nm high-kappa metal-gate (H kappa MG) CMOS technology with macro area of 1058.22 x 374.76 mu m(2). Error-free full functionality is achieved from 0.9 down to 0.5 V (limited by read VMIN) without redundancy. The low-swing GRBL reduces dynamic power by 6.5% (8.0%) at 0.9 V (0.6 V). The VTWA improves the write VMIN by 75 mV (from 0.525 to 0.45 V). The measured maximum operation frequency is 735 MHz (20 MHz) at 0.9 V (0.5 V), TT corner, 25(omicron). | en_US |
dc.language.iso | en_US | en_US |
dc.subject | Low voltage | en_US |
dc.subject | low power | en_US |
dc.subject | static random access memory (SRAM) | en_US |
dc.subject | write-assist | en_US |
dc.subject | power-gating | en_US |
dc.subject | near-threshold | en_US |
dc.title | A 0.5-V 28-nm 256-kb Mini-Array Based 6T SRAM With Vtrip-Tracking Write-Assist | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/TCSI.2017.2681738 | en_US |
dc.identifier.journal | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | en_US |
dc.citation.volume | 64 | en_US |
dc.citation.spage | 1791 | en_US |
dc.citation.epage | 1802 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000404294900015 | en_US |
顯示於類別: | 期刊論文 |