Full metadata record
DC FieldValueLanguage
dc.contributor.authorZhao, Yanen_US
dc.contributor.authorChen, Zuow-Zunen_US
dc.contributor.authorDu, Yuanen_US
dc.contributor.authorLi, Yileien_US
dc.contributor.authorAl Hadi, Richarden_US
dc.contributor.authorVirbila, Gabrielen_US
dc.contributor.authorXu, Yinuoen_US
dc.contributor.authorKim, Yanghyoen_US
dc.contributor.authorTang, Adrianen_US
dc.contributor.authorReck, Theodore J.en_US
dc.contributor.authorChang, Mau-Chung Franken_US
dc.date.accessioned2018-08-21T05:54:21Z-
dc.date.available2018-08-21T05:54:21Z-
dc.date.issued2016-12-01en_US
dc.identifier.issn0018-9200en_US
dc.identifier.urihttp://dx.doi.org/10.1109/JSSC.2016.2601614en_US
dc.identifier.urihttp://hdl.handle.net/11536/145839-
dc.description.abstractThis paper presents the design and characterization of a 0.56 THz frequency synthesizer implemented in standard 65 nm CMOS technology. Its front end consists of triple-push Colpitts oscillators (TPCOs), followed by the first and second stage injection locking frequency dividers (ILFDs) and a divide-by-16 chain. TPCOs are used to triple their fundamental frequencies to 0.53-0.56 THz, while ILFDs and the subsequent divider chain are used to divide such frequencies to 2.7-2.9 GHz. Its back end consists of separate frequency and phase-locked loops with unique CMOS circuit designs to accomplish the desirable frequency/phase locking, including: 1) band-selection inductor switches; 2) simultaneous bulk voltage tuning over TPCOs and the first ILFD; and 3) a dual port injection architecture for the first ILFD. The resultant prototype realizes a 21 GHz frequency locking range with phase noise lower than -74 dBc/Hz at 1 MHz offset, and consumes 174 mW dc power.en_US
dc.language.isoen_USen_US
dc.subjectBulk voltage tuningen_US
dc.subjectfrequency synthesizeren_US
dc.subjectharmonic oscillatoren_US
dc.subjectinjection lockingen_US
dc.subjectphase-locked loop (PLL)en_US
dc.subjectsubsampling phase detectoren_US
dc.subjectterahertzen_US
dc.subjecttriple-push Colpitts oscillator (TPCO)en_US
dc.subjecttriple-push oscillator (TPO)en_US
dc.titleA 0.56 THz Phase-Locked Frequency Synthesizer in 65 nm CMOS Technologyen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/JSSC.2016.2601614en_US
dc.identifier.journalIEEE JOURNAL OF SOLID-STATE CIRCUITSen_US
dc.citation.volume51en_US
dc.citation.spage3005en_US
dc.citation.epage3019en_US
dc.contributor.department交大名義發表zh_TW
dc.contributor.departmentNational Chiao Tung Universityen_US
dc.identifier.wosnumberWOS:000390420300018en_US
Appears in Collections:Articles