Impact of Shielding Line on CDM ESD Robustness of Core Circuits in a 65-nm CMOS Process

Abstract

The charged-device-model (CDM) ESD robustness of core circuit with/without the shielding line was studied in a 65nm CMOS process. Verified in silicon chip, the CDM ESD robustness of core circuit with the shielding line was degraded. The damage mechanism and failure location of the test circuits were investigated in this work.