Impact of Shielding Line on CDM ESD Robustness of Core Circuits in a 65-nm CMOS Process

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Ker, Ming-Dou	en_US
dc.contributor.author	Lin, Chun-Yu	en_US
dc.contributor.author	Chang, Tang-Long	en_US
dc.date.accessioned	2014-12-08T15:20:29Z	-
dc.date.available	2014-12-08T15:20:29Z	-
dc.date.issued	2011	en_US
dc.identifier.isbn	978-1-4244-9111-7	en_US
dc.identifier.uri	http://hdl.handle.net/11536/14586	-
dc.description.abstract	The charged-device-model (CDM) ESD robustness of core circuit with/without the shielding line was studied in a 65nm CMOS process. Verified in silicon chip, the CDM ESD robustness of core circuit with the shielding line was degraded. The damage mechanism and failure location of the test circuits were investigated in this work.	en_US
dc.language.iso	en_US	en_US
dc.subject	Charged-device model (CDM)	en_US
dc.subject	ESD	en_US
dc.subject	shielding line	en_US
dc.title	Impact of Shielding Line on CDM ESD Robustness of Core Circuits in a 65-nm CMOS Process	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	2011 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS)	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000295322100123	-
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