A Hardware-Efficient VLSI Implementation of a 4-Channel ICA Processor for Biomedical Signal Measurement

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Chen, Chiu-Kuo	en_US
dc.contributor.author	Chua, Ericson	en_US
dc.contributor.author	Fu, Chih-Chung	en_US
dc.contributor.author	Tseng, Shao-Yen	en_US
dc.contributor.author	Fang, Wai-Chi	en_US
dc.date.accessioned	2014-12-08T15:20:30Z	-
dc.date.available	2014-12-08T15:20:30Z	-
dc.date.issued	2011	en_US
dc.identifier.isbn	978-1-4244-8712-7	en_US
dc.identifier.uri	http://hdl.handle.net/11536/14604	-
dc.description.abstract	This paper presents a 4-channel ICA implementation in the separation of EEG signals for on-line monitoring and analysis of brain functionalities. A novel ICA architecture utilizing mixed sequential, pipelined, and parallel processing units and employing interleaved and circular-based RAM modules to achieve hardware-efficient design is presented. The ICA processor is fabricated using UMC 90nm High-Vt CMOS technology.	en_US
dc.language.iso	en_US	en_US
dc.title	A Hardware-Efficient VLSI Implementation of a 4-Channel ICA Processor for Biomedical Signal Measurement	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	IEEE INTERNATIONAL CONFERENCE ON CONSUMER ELECTRONICS (ICCE 2011)	en_US
dc.citation.spage	607	en_US
dc.citation.epage	608	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000295128300304	-
顯示於類別：	會議論文