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dc.contributor.authorLin, Ding-Guoen_US
dc.contributor.authorLu, Bing-Hsunen_US
dc.contributor.authorChiueh, Hermingen_US
dc.date.accessioned2014-12-08T15:20:30Z-
dc.date.available2014-12-08T15:20:30Z-
dc.date.issued2010en_US
dc.identifier.isbn978-1-4244-6470-8en_US
dc.identifier.urihttp://hdl.handle.net/11536/14607-
dc.description.abstractIn this paper, a glitch-free DLL-based clock generator using a feedback-switching detector is proposed for a programmable power management system. The proposed circuitry utilizes feedback switching detectors to eliminate undesired glitch problem which is generated by switching feedback stage of a DLL. The clock generator can generate clock signals ranging from 100MHz to 1.6GHz. The peak to peak jitter is 23.168ps and power consumption is 37.8mW at 1.6GHz. The proposed clock generator is implemented in TSMC 0.18 mu m process and occupies only 0.039 mm(2) which is suitable for the power management systems.en_US
dc.language.isoen_USen_US
dc.titleAn 100MHz to 1.6GHz DLL-Based Clock Generator Using a Feedback-Switching Detectoren_US
dc.typeProceedings Paperen_US
dc.identifier.journalPROCEEDINGS OF THE 2010 18TH IEEE/IFIP INTERNATIONAL CONFERENCE ON VLSI AND SYSTEM-ON-CHIPen_US
dc.citation.spage101en_US
dc.citation.epage104en_US
dc.contributor.department電機工程學系zh_TW
dc.contributor.departmentDepartment of Electrical and Computer Engineeringen_US
dc.identifier.wosnumberWOS:000295220400018-
Appears in Collections:Conferences Paper