標題: A 41.3/26.7 pJ per Neuron Weight RBM Processor Supporting On-Chip Learning/Inference for IoT Applications
作者: Tsai, Chang-Hung
Yu, Wan-Ju
Wong, Wing Hung
Lee, Chen-Yi
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Low-power design;machine learning;memory bandwidth reduction;non-linear functions;restricted Boltzmann machine (RBM)
公開日期: 1-Oct-2017
摘要: An energy-efficient restricted Boltzmann machine (RBM) processor (RBM-P) supporting on-chip learning and inference is proposed for machine learning and Internet of Things (IoT) applications in this paper. To train a neural network (NN) model, the RBM structure is applied to supervised and unsupervised learning, and a multi-layer NN can be constructed and initialized by stacking multiple RBMs. Featuring NN model reduction for external memory bandwidth saving, low power neuron binarizer (LPNB) with dynamic clock gating and area-efficient NN-like activation function calculators for power reduction, user-defined connection map (UDCM) for both computation time and bandwidth saving, and early stopping (ES) mechanism for learning process, the proposed system integrates 32 RBM cores with maximal 4k neurons per layer and 128 candidates per sample for machine learning applications. Implemented in 65nm CMOS technology, the proposed RBM-P chip costs 2.2 M gates and 128 kB SRAM with 8.8 mm(2) area. Operated at 1.2 V and 210 MHz, this chip achieves 7.53G neuron weights (NWs) and 11.63G NWs per second with 41.3 and 26.7 pJ per NW for learning and inference, respectively.
URI: http://dx.doi.org/10.1109/JSSC.2017.2715171
http://hdl.handle.net/11536/146136
ISSN: 0018-9200
DOI: 10.1109/JSSC.2017.2715171
期刊: IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume: 52
起始頁: 2601
結束頁: 2612
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