A 1 V 175 mu W 94.6 dB SNDR 25 kHz Bandwidth Delta-Sigma Modulator Using Segmented Integration Techniques

Abstract

A 2-1 MASH switched-capacitor delta-sigma modulator was fabricated using a 65 nm CMOS technology. We constantly alternate the circuit configurations of its internal integrators to optimize power consumption. The integrators are accelerated only when they are in crucial integration cycle. Operating at 5 MS/s sampling rate, this chip consumes 175 mu W from a 1 V supply. Assuming a 25 kHz signal bandwidth, it achieves 96.1 dB SNR, 94.6 dB SNDR, and 98.5 dB DR. Its active area is 1.13 x 0.34 mm(2).