Blockage and Voltage Island-Aware Dual-VDD Buffered Tree Construction Under Fixed Buffer Locations

Abstract

Due to the need of low power methodology in VLSI and SoC designs, voltage island architecture is attracting attentions in design community. However, the corresponding EDA tools development for voltage-island-aware buffered renting is still very few. Recent related studies focused on applying dual V-dd buffers in routing tree construction, however it cannot be applied on a design using voltage island architecture due to the restriction on the ordering of low and high V-dd buffers and the lack of level converter consideration. This paper presents approaches to solving the buffer insertion and level converter assignment problem in the presence of voltage island in a low-power design; especially under the fixed buffer locations. We have implemented and modified one state-of-the-art graph-based approach for this specific routing problem and applied our efficient heuristics (one of them is based on the selection of Steiner points) to further improve the performance, considering the assignment of buffers and level converters/shifters simultaneously. The experimental results show that we can obtain massive speedup over modified prior approach, and even with lower power and delay. Furthermore, as the number of sinks increases, our approach can effectively find feasible Solutions, while modified prior approach cannot find solutions within a reasonable runtime.