完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Chou, Pei-Yuan | en_US |
dc.contributor.author | Wu, I-Chen | en_US |
dc.contributor.author | Lin, Jai-Wei | en_US |
dc.contributor.author | Lin, Xuan-Yu | en_US |
dc.contributor.author | Chen, Tien-Fu | en_US |
dc.contributor.author | Lin, Tay-Jyi | en_US |
dc.contributor.author | Wang, Jinn-Shyan | en_US |
dc.date.accessioned | 2018-08-21T05:56:38Z | - |
dc.date.available | 2018-08-21T05:56:38Z | - |
dc.date.issued | 2015-01-01 | en_US |
dc.identifier.issn | 2162-7541 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/146453 | - |
dc.description.abstract | We propose to use a canary circuit with dynamic trip-point sensing scheme to replace ECC check bits and related circuits in conventional DVS caches for reducing area overhead and to enable deeper voltage scaling for reducing power consumption. With the canary circuit, a variable-cycle access controller can easily deal with an overlong delay without pre-allocating Vcc headroom for covering the droop voltage. Applying all the proposed delay-fault-prevention design techniques together can lead to a cost-effective and power-efficient DVS cache. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Low-Cost Low-Power Droop-Voltage-Aware Delay-Fault-Prevention Designs for DVS Caches | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | PROCEEDINGS OF 2015 IEEE 11TH INTERNATIONAL CONFERENCE ON ASIC (ASICON) | en_US |
dc.contributor.department | 資訊工程學系 | zh_TW |
dc.contributor.department | Department of Computer Science | en_US |
dc.identifier.wosnumber | WOS:000398709000176 | en_US |
顯示於類別: | 會議論文 |