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dc.contributor.authorChou, Pei-Yuanen_US
dc.contributor.authorWu, I-Chenen_US
dc.contributor.authorLin, Jai-Weien_US
dc.contributor.authorLin, Xuan-Yuen_US
dc.contributor.authorChen, Tien-Fuen_US
dc.contributor.authorLin, Tay-Jyien_US
dc.contributor.authorWang, Jinn-Shyanen_US
dc.date.accessioned2018-08-21T05:56:38Z-
dc.date.available2018-08-21T05:56:38Z-
dc.date.issued2015-01-01en_US
dc.identifier.issn2162-7541en_US
dc.identifier.urihttp://hdl.handle.net/11536/146453-
dc.description.abstractWe propose to use a canary circuit with dynamic trip-point sensing scheme to replace ECC check bits and related circuits in conventional DVS caches for reducing area overhead and to enable deeper voltage scaling for reducing power consumption. With the canary circuit, a variable-cycle access controller can easily deal with an overlong delay without pre-allocating Vcc headroom for covering the droop voltage. Applying all the proposed delay-fault-prevention design techniques together can lead to a cost-effective and power-efficient DVS cache.en_US
dc.language.isoen_USen_US
dc.titleLow-Cost Low-Power Droop-Voltage-Aware Delay-Fault-Prevention Designs for DVS Cachesen_US
dc.typeProceedings Paperen_US
dc.identifier.journalPROCEEDINGS OF 2015 IEEE 11TH INTERNATIONAL CONFERENCE ON ASIC (ASICON)en_US
dc.contributor.department資訊工程學系zh_TW
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.identifier.wosnumberWOS:000398709000176en_US
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