Variation-Aware and Adaptive-Latency Accesses for Reliable Low Voltage Caches

Abstract

Contemporary cache is known for consuming a large part of total power in microprocessors. Voltage scaling had been used to reduce the power consumption of the cache. However, due to the impact of variations, SRAM cells of the cache could potentially fail when voltage dropping. To against variations, we need to increase the supply voltage for the safety margin, thus the cache costs large energy consumption. For eliminating the voltage safety margin, some prior works for SRAM failure tolerance designs were proposed. These schemes will result in worse energy consumption and cannot deal with dynamic variations. They still have a safety margin to resist dynamic variations. With the supply voltage scaling down, we find out that the major reason of failures is that some slow cells have longer latency. We call these cell faults as "latency fault". If each cache line can be accessed in an appropriate access time, the slower cells could be reused but not disable them. We propose a VAL-Cache adapting the access time to tolerate latency faults and which is able to scale down the voltage. And we also propose the latency-fault detector to detect latency faults at run-time so as to tolerate both static and dynamic variations. Our experimental results on Mibench and 0xbench benchmarks demonstrate that the energy consumption can be reduced 10%similar to 18% in average at a cost of acceptable performance loss.