標題: | Zero-Counting and Adaptive-Latency Cache Using a Voltage-Guardband Breakthrough for Energy-Efficient Operations |
作者: | Wang, Po-Hao Cheng, Wei-Chung Yu, Yung-Hui Kao, Tang-Chieh Tsai, Chi-Lun Chang, Pei-Yao Lin, Tay-Jyi Wang, Jinn-Shyan Chen, Tien-Fu 資訊工程學系 Department of Computer Science |
關鍵字: | Adaptive access time;cache memory;energy efficiency;fault tolerance;voltage-guardband elimination |
公開日期: | 十月-2016 |
摘要: | In modern embedded processor systems, energy efficiency is a critical issue. Unfortunately, to avoid cache memory (SRAM) faults from dynamic variations, caches generally operate at an elevated voltage to build a safety guardband that decreases energy efficiency. To address this issue, tolerating SRAM faults to eliminate the safety of a guardband without frequency scaling may be a viable solution. This study investigates the characteristics of low-voltage 8 T SRAM faults and demonstrates that most SRAM faults are typically caused by insufficient access times with variation effects and significantly reduced voltages. Thus, we propose an access-time fault-tolerant cache design based on a type of 8 T SRAM known as zero-counting and adaptive-latency cache (ZCAL cache), which can tolerate numerous access-time faults. ZCAL caches detect access-time faults dynamically using a lightweight error detection code ("0" counting) because access-time faults occur only when reading "0" bits on the 8 T SRAM; the cache then adapts its access time to tolerate the access-time faults with new cache management processes. With the ZCAL cache, the experimental results from the MiBench benchmarks indicate that the energy efficiency is improved by 17% on average and that the energy consumption is reduced by 22% from 0.76 to 0.63 V. |
URI: | http://dx.doi.org/10.1109/TCSII.2016.2539038 http://hdl.handle.net/11536/132658 |
ISSN: | 1549-7747 |
DOI: | 10.1109/TCSII.2016.2539038 |
期刊: | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS |
Volume: | 63 |
Issue: | 10 |
起始頁: | 969 |
結束頁: | 973 |
顯示於類別: | 期刊論文 |