完整後設資料紀錄
DC 欄位語言
dc.contributor.authorWang, Po-Haoen_US
dc.contributor.authorCheng, Wei-Chungen_US
dc.contributor.authorYu, Yung-Huien_US
dc.contributor.authorKao, Tang-Chiehen_US
dc.contributor.authorTsai, Chi-Lunen_US
dc.contributor.authorChang, Pei-Yaoen_US
dc.contributor.authorLin, Tay-Jyien_US
dc.contributor.authorWang, Jinn-Shyanen_US
dc.contributor.authorChen, Tien-Fuen_US
dc.date.accessioned2017-04-21T06:56:40Z-
dc.date.available2017-04-21T06:56:40Z-
dc.date.issued2016-10en_US
dc.identifier.issn1549-7747en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TCSII.2016.2539038en_US
dc.identifier.urihttp://hdl.handle.net/11536/132658-
dc.description.abstractIn modern embedded processor systems, energy efficiency is a critical issue. Unfortunately, to avoid cache memory (SRAM) faults from dynamic variations, caches generally operate at an elevated voltage to build a safety guardband that decreases energy efficiency. To address this issue, tolerating SRAM faults to eliminate the safety of a guardband without frequency scaling may be a viable solution. This study investigates the characteristics of low-voltage 8 T SRAM faults and demonstrates that most SRAM faults are typically caused by insufficient access times with variation effects and significantly reduced voltages. Thus, we propose an access-time fault-tolerant cache design based on a type of 8 T SRAM known as zero-counting and adaptive-latency cache (ZCAL cache), which can tolerate numerous access-time faults. ZCAL caches detect access-time faults dynamically using a lightweight error detection code ("0" counting) because access-time faults occur only when reading "0" bits on the 8 T SRAM; the cache then adapts its access time to tolerate the access-time faults with new cache management processes. With the ZCAL cache, the experimental results from the MiBench benchmarks indicate that the energy efficiency is improved by 17% on average and that the energy consumption is reduced by 22% from 0.76 to 0.63 V.en_US
dc.language.isoen_USen_US
dc.subjectAdaptive access timeen_US
dc.subjectcache memoryen_US
dc.subjectenergy efficiencyen_US
dc.subjectfault toleranceen_US
dc.subjectvoltage-guardband eliminationen_US
dc.titleZero-Counting and Adaptive-Latency Cache Using a Voltage-Guardband Breakthrough for Energy-Efficient Operationsen_US
dc.identifier.doi10.1109/TCSII.2016.2539038en_US
dc.identifier.journalIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFSen_US
dc.citation.volume63en_US
dc.citation.issue10en_US
dc.citation.spage969en_US
dc.citation.epage973en_US
dc.contributor.department資訊工程學系zh_TW
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.identifier.wosnumberWOS:000385411500013en_US
顯示於類別:期刊論文