完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Wang, Po-Hao | en_US |
dc.contributor.author | Cheng, Wei-Chung | en_US |
dc.contributor.author | Yu, Yung-Hui | en_US |
dc.contributor.author | Kao, Tang-Chieh | en_US |
dc.contributor.author | Tsai, Chi-Lun | en_US |
dc.contributor.author | Chang, Pei-Yao | en_US |
dc.contributor.author | Lin, Tay-Jyi | en_US |
dc.contributor.author | Wang, Jinn-Shyan | en_US |
dc.contributor.author | Chen, Tien-Fu | en_US |
dc.date.accessioned | 2017-04-21T06:56:40Z | - |
dc.date.available | 2017-04-21T06:56:40Z | - |
dc.date.issued | 2016-10 | en_US |
dc.identifier.issn | 1549-7747 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/TCSII.2016.2539038 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/132658 | - |
dc.description.abstract | In modern embedded processor systems, energy efficiency is a critical issue. Unfortunately, to avoid cache memory (SRAM) faults from dynamic variations, caches generally operate at an elevated voltage to build a safety guardband that decreases energy efficiency. To address this issue, tolerating SRAM faults to eliminate the safety of a guardband without frequency scaling may be a viable solution. This study investigates the characteristics of low-voltage 8 T SRAM faults and demonstrates that most SRAM faults are typically caused by insufficient access times with variation effects and significantly reduced voltages. Thus, we propose an access-time fault-tolerant cache design based on a type of 8 T SRAM known as zero-counting and adaptive-latency cache (ZCAL cache), which can tolerate numerous access-time faults. ZCAL caches detect access-time faults dynamically using a lightweight error detection code ("0" counting) because access-time faults occur only when reading "0" bits on the 8 T SRAM; the cache then adapts its access time to tolerate the access-time faults with new cache management processes. With the ZCAL cache, the experimental results from the MiBench benchmarks indicate that the energy efficiency is improved by 17% on average and that the energy consumption is reduced by 22% from 0.76 to 0.63 V. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | Adaptive access time | en_US |
dc.subject | cache memory | en_US |
dc.subject | energy efficiency | en_US |
dc.subject | fault tolerance | en_US |
dc.subject | voltage-guardband elimination | en_US |
dc.title | Zero-Counting and Adaptive-Latency Cache Using a Voltage-Guardband Breakthrough for Energy-Efficient Operations | en_US |
dc.identifier.doi | 10.1109/TCSII.2016.2539038 | en_US |
dc.identifier.journal | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | en_US |
dc.citation.volume | 63 | en_US |
dc.citation.issue | 10 | en_US |
dc.citation.spage | 969 | en_US |
dc.citation.epage | 973 | en_US |
dc.contributor.department | 資訊工程學系 | zh_TW |
dc.contributor.department | Department of Computer Science | en_US |
dc.identifier.wosnumber | WOS:000385411500013 | en_US |
顯示於類別: | 期刊論文 |