標題: Low-Cost Low-Power Droop-Voltage-Aware Delay-Fault-Prevention Designs for DVS Caches
作者: Chou, Pei-Yuan
Wu, I-Chen
Lin, Jai-Wei
Lin, Xuan-Yu
Chen, Tien-Fu
Lin, Tay-Jyi
Wang, Jinn-Shyan
資訊工程學系
Department of Computer Science
公開日期: 1-Jan-2015
摘要: We propose to use a canary circuit with dynamic trip-point sensing scheme to replace ECC check bits and related circuits in conventional DVS caches for reducing area overhead and to enable deeper voltage scaling for reducing power consumption. With the canary circuit, a variable-cycle access controller can easily deal with an overlong delay without pre-allocating Vcc headroom for covering the droop voltage. Applying all the proposed delay-fault-prevention design techniques together can lead to a cost-effective and power-efficient DVS cache.
URI: http://hdl.handle.net/11536/146453
ISSN: 2162-7541
期刊: PROCEEDINGS OF 2015 IEEE 11TH INTERNATIONAL CONFERENCE ON ASIC (ASICON)
Appears in Collections:Conferences Paper