標題: A 0.4V 53dB SNDR 250 MS/s Time-Based CT Delta Sigma Analog to Digital Converter
作者: Chen, Hung-Kai
Chen, Wei-Zen
Ren Zhiyuan
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: ULV;ULP;CT-Delta Sigma ADC
公開日期: 1-Jan-2015
摘要: This paper presents the design of an ultra-low voltage (ULV), time-based, continuous-time Delta Sigma analog-to-digital data converter. By replacing the 2nd stage integrator with frequency-calibrated voltage bootstrapping VCO, it circumvents ULV design challenges while achieving a signal bandwidth up to 2 MHz. Back-gate adder, voltage amplifier, and bootstrapping logic cells are also proposed to enable 250 MHz sampling rate operation. The measured peak SNDR is 53 dB under a supply voltage of 0.4 V. The whole ADC consumes 526 mu W. Fabricated in a 90 nm CMOS process, the core area is 0.08 mm(2).
URI: http://hdl.handle.net/11536/146454
ISSN: 2162-7541
期刊: PROCEEDINGS OF 2015 IEEE 11TH INTERNATIONAL CONFERENCE ON ASIC (ASICON)
Appears in Collections:Conferences Paper