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dc.contributor.authorTsai, Wen-Jeren_US
dc.contributor.authorLin, W. L.en_US
dc.contributor.authorCheng, C. C.en_US
dc.contributor.authorKu, S. H.en_US
dc.contributor.authorChou, Y. L.en_US
dc.contributor.authorLiu, Lenvisen_US
dc.contributor.authorHwang, S. W.en_US
dc.contributor.authorLu, T. C.en_US
dc.contributor.authorChen, K. C.en_US
dc.contributor.authorWang, Tahuien_US
dc.contributor.authorLu, Chih-Yuanen_US
dc.date.accessioned2018-08-21T05:56:39Z-
dc.date.available2018-08-21T05:56:39Z-
dc.date.issued2016-01-01en_US
dc.identifier.issn2380-9248en_US
dc.identifier.urihttp://hdl.handle.net/11536/146471-
dc.description.abstractVt instability caused by grain-boundary trap (GBT) in the poly-crystalline silicon (poly-Si) channel of a 3D NAND string are comprehensively studied. Experimental results reveal that trapping/detrapping of GBT would cause transient cell current with a time constant of lOus or longer, and this transient is strongly affected by the bias history. Sensing offset between program/erase verify (PV/EV) and read (RD) results in "pseudo" charge loss/gain that reduces the sensing margin. Modified EV, PV, or RD bias schemes are suggested to mitigate this effect.en_US
dc.language.isoen_USen_US
dc.titlePolycrystalline-Silicon Channel Trap Induced Transient Read Instability in a 3D NAND Flash Cell Stringen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2016 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM)en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000399108800070en_US
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