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dc.contributor.authorShyu, Ting-Yuen_US
dc.contributor.authorSu, Bo-Yuen_US
dc.contributor.authorLin, Tay-Jyien_US
dc.contributor.authorYeh, Chingweien_US
dc.contributor.authorWang, Jinn-Shyanen_US
dc.contributor.authorChen, Tien-Fuen_US
dc.date.accessioned2018-08-21T05:56:48Z-
dc.date.available2018-08-21T05:56:48Z-
dc.date.issued2016-01-01en_US
dc.identifier.urihttp://hdl.handle.net/11536/146658-
dc.description.abstractVery-long-instruction-word (VLIW) architectures are widely adopted in high-performance and low-power digital signal processors (DSP) due to their simplicity from extensive software optimizations. However, their poor code density (usually > 2X code size for a given application) and corresponding instruction accesses can overwhelm the energy savings on DSP datapaths. This paper presents variable-length VLIW ((VLIW)-I-2), where the unused condition codes, operands/operand scope, and reduced range of immediate variables of TI C64x+ DSP are exploited to improve the code density. The static grouping and run-time dispersal schemes of the variable-length instructions in a VLIW packet are described. In our experiments, 21% code sizes are saved in average for MiBench kernels. The hardware overhead is only similar to 5%.en_US
dc.language.isoen_USen_US
dc.titleVariable-Length VLIW Encoding for Code Size Reduction in Embedded Processorsen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2016 29TH IEEE INTERNATIONAL SYSTEM-ON-CHIP CONFERENCE (SOCC)en_US
dc.citation.spage296en_US
dc.citation.epage299en_US
dc.contributor.department資訊工程學系zh_TW
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.identifier.wosnumberWOS:000403576000052en_US
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