完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Shyu, Ting-Yu | en_US |
dc.contributor.author | Su, Bo-Yu | en_US |
dc.contributor.author | Lin, Tay-Jyi | en_US |
dc.contributor.author | Yeh, Chingwei | en_US |
dc.contributor.author | Wang, Jinn-Shyan | en_US |
dc.contributor.author | Chen, Tien-Fu | en_US |
dc.date.accessioned | 2018-08-21T05:56:48Z | - |
dc.date.available | 2018-08-21T05:56:48Z | - |
dc.date.issued | 2016-01-01 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/146658 | - |
dc.description.abstract | Very-long-instruction-word (VLIW) architectures are widely adopted in high-performance and low-power digital signal processors (DSP) due to their simplicity from extensive software optimizations. However, their poor code density (usually > 2X code size for a given application) and corresponding instruction accesses can overwhelm the energy savings on DSP datapaths. This paper presents variable-length VLIW ((VLIW)-I-2), where the unused condition codes, operands/operand scope, and reduced range of immediate variables of TI C64x+ DSP are exploited to improve the code density. The static grouping and run-time dispersal schemes of the variable-length instructions in a VLIW packet are described. In our experiments, 21% code sizes are saved in average for MiBench kernels. The hardware overhead is only similar to 5%. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Variable-Length VLIW Encoding for Code Size Reduction in Embedded Processors | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2016 29TH IEEE INTERNATIONAL SYSTEM-ON-CHIP CONFERENCE (SOCC) | en_US |
dc.citation.spage | 296 | en_US |
dc.citation.epage | 299 | en_US |
dc.contributor.department | 資訊工程學系 | zh_TW |
dc.contributor.department | Department of Computer Science | en_US |
dc.identifier.wosnumber | WOS:000403576000052 | en_US |
顯示於類別: | 會議論文 |