標題: Scaling of Gate Dielectric on Ge Substrate
作者: Chan, Yung-Hsiang
Tsui, Bing-Yue
電機學院
電子工程學系及電子研究所
College of Electrical and Computer Engineering
Department of Electronics Engineering and Institute of Electronics
公開日期: 1-一月-2017
摘要: Scaling of Hf-based and Zr-based gate dielectric stack on Ge is investigated. Effects of dielectric thickness and thermal budget on the MOS device characteristics are studied. Tradeoff among effective oxide thickness (EOT), leakage current density (J(G)), interface state density (D-it), and hysteresis are observed and discussed. With the same HfO2 and ZrO2 thickness, the ZrO2 samples exhibit lower D-it and smaller hysteresis but slightly higher J(G). The crystallized ZrO2 exhibits the best J(G)-EOT performance. However, as the EOT becomes thinner than 0.8 nm, it is hard to lower D-it to 1x10 (12) eV(-1)cm(-2). According to these results, novel techniques for Ge surface passivation and ZrO2 crystallization are required.
URI: http://hdl.handle.net/11536/146754
ISSN: 1930-8868
期刊: 2017 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATION (VLSI-TSA)
顯示於類別:會議論文