Investigation and Comparison of Design Space for Ultra-Thin-Body GeOI/SOI Negative Capacitance FETs

完整后设资料纪录

DC 栏位	值	语言
dc.contributor.author	Lee, Ho-Pei	en_US
dc.contributor.author	Yu, Chien-Lin	en_US
dc.contributor.author	You, Wei-Xiang	en_US
dc.contributor.author	Su, Pin	en_US
dc.date.accessioned	2018-08-21T05:56:52Z	-
dc.date.available	2018-08-21T05:56:52Z	-
dc.date.issued	2017-01-01	en_US
dc.identifier.issn	1930-8868	en_US
dc.identifier.uri	http://hdl.handle.net/11536/146759	-
dc.language.iso	en_US	en_US
dc.title	Investigation and Comparison of Design Space for Ultra-Thin-Body GeOI/SOI Negative Capacitance FETs	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	2017 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATION (VLSI-TSA)	en_US
dc.contributor.department	电子工程学系及电子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000408991800027	en_US
显示于类别：	Conferences Paper

APA	Lee, H., Yu, C., You, W., & Su, P. (2017). Investigation and Comparison of Design Space for Ultra-Thin-Body GeOI/SOI Negative Capacitance FETs. WOS:000408991800027.
Bibtex	@article{Lee2017Investigation, title={Investigation and Comparison of Design Space for Ultra-Thin-Body GeOI/SOI Negative Capacitance FETs}, author={Lee, Ho-Pei and Yu, Chien-Lin and You, Wei-Xiang and Su, Pin}, journal={WOS:000408991800027}, year={2017}, url={https://ir.lib.nycu.edu.tw/handle/11536/146759?locale=zh_CN&mode=full}, }