Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Liu, Wen-Hao | en_US |
dc.contributor.author | Kao, Wei-Chun | en_US |
dc.contributor.author | Li, Yih-Lang | en_US |
dc.contributor.author | Chao, Kai-Yuan | en_US |
dc.date.accessioned | 2018-08-21T05:56:53Z | - |
dc.date.available | 2018-08-21T05:56:53Z | - |
dc.date.issued | 2010-01-01 | en_US |
dc.identifier.issn | 0738-100X | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/146775 | - |
dc.description.abstract | Modern global routers use various routing methods to improve routing speed and the quality. Maze routing is the most time-consuming process for existing global routing algorithms. This paper presents two bounded-length maze routing (BLMR) algorithms (optimal-BLMR and heuristic-BLMR) to perform much faster routing than traditional maze routing algorithms. The proposed sequential global router, which adopts a heuristic-BLMR, identifies less-wirelength routing results with less runtime than state-of-the-art global routers. This study also proposes a parallel multi-threaded collision-aware global router based on a previous sequential global router. Unlike the conventional partition-based concurrency strategy, the proposed algorithm uses a task-based concurrency strategy. Experimental results reveal that the proposed sequential global router uses less wirelength and runs about 1.9X to 18.67X faster than other state-of-the-art global routers. Compared to the proposed sequential global router, the proposed parallel global router yields almost the same routing quality with average 2.71and 3.12-fold speedup on overflow-free and hard-to-route benchmarks, respectively, when running on an Intel quad-core system. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | Global routing | en_US |
dc.subject | maze routing | en_US |
dc.subject | multi-threaded | en_US |
dc.title | Multi-Threaded Collision-Aware Global Routing with Bounded-Length Maze Routing | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | PROCEEDINGS OF THE 47TH DESIGN AUTOMATION CONFERENCE | en_US |
dc.citation.spage | 200 | en_US |
dc.citation.epage | 205 | en_US |
dc.contributor.department | 資訊工程學系 | zh_TW |
dc.contributor.department | Department of Computer Science | en_US |
dc.identifier.wosnumber | WOS:000409973500038 | en_US |
Appears in Collections: | Conferences Paper |