良率考量的全域繞線建立於隨機關鍵區域分析平台上

Abstract

在現今超大型積體電路的設計中，因為製程縮小而使得良率相關的問題也越來越嚴重。使得良率下降的原因有很多，隨機粒子所造成的短路與斷路就是其中一個主要的原因。在現今的流程中，我們需要等到繞線全部完成之後，才能採取一些最佳化的方法來解決這個問題，但是在這個階段可以改善的成效也不甚良好。在本篇論文中，測試例子為ISPD2007全域繞線比賽時所提供的檔案。我們將藉由一個有效的機率模擬方式，讓我們可以在全域繞線的階段時預測隨機粒子有可能造成問題的區域，並利用一些繞線的技巧來降低短路或斷路發生的機率，以此來提高電路的良率。我們將先用FLUTE程式把電路轉為一組組兩點相連的問題，再從小區域往大區域的趨勢把所有點連結，最後再把違反條件的繞線區域拔除重繞，以此來完成一組預期的全域繞線結果。實驗結果顯示，高密度關鍵區域的數量相較於NTHU-Route有明顯的減少。

In modern VLSI design, the semiconductor technology has advanced toward the nanometer era. Although this advancement reduces circuit power and area, it also has many side effect issues such as the decrease in yield and reliability. There are many reasons that cause the reduction in yield and reliability and one of them is critical area problem. Critical areas are regions in which circuits are prone to short or open if random particle landed in those regions. In today’s design flow, industries resolve critical area problem when design flow reaches detail routing stage. However, the improvements obtained in detail routing stage are minimal. If design flow can consider critical area problem in earlier stage, the improvement in terms of increasing yield and reliability is much greater. The benchmarks from ISPD 2007 and ISPD 2008 contest are used to verify the effectiveness of our approach. This thesis proposes an accurate probability prediction model to estimate the critical area in global routing stage and apply certain algorithms to decrease the possibility of generating critical area map in detailed routing stage. We use external algorithm FLUTE to generate Steiner Trees then apply certain routing techniques to resolve congestion and critical area issue. According to the experimental results, the number of most dense critical area has a significant reduction compare to NTHU-Route.