減少橋式錯誤的全域繞線與線軌指派法

Abstract

隨著VLSI (very-large-scale integration 超大型積體電路) 製程愈來愈進步，「為製造而設計」(Design for manufacturing, DFM)變的是一個大家積極著手研究的問題。其中隨機瑕疵（random defect）的臨界區域(Critical area)就是一個被大量研究的議題。隨機瑕疵的影響並不會隨著製程進步而縮小，因此它變成是影響良率的重要關鍵。在設計流程中，繞線是一個很適合處理隨機瑕疵問題的階段，因為繞線時可排列實體線路，而實體線路是最容易發生錯誤的地方。本論文提出了一個考量隨機瑕疵的繞線流程，流程包含了全球繞線以及線軌指派法。在線軌指派的同時也會將包含錯誤機率的成本函式的值降到最低來達到減少隨機瑕疵的效果。實驗結果顯示提出的繞線流程花費的時間較以前的實驗少，在使用蒙地卡羅模擬法時也達到與先前的論文相比最多10％的錯誤減低。

As VLSI scaling down and feature size shrinking, design for manufacturing (DFM) has becoming a widely studied problem. The critical area for random defects is a heavily surveyed DFM problem. The effect of random defects, which do not shrink with feature size, has become one of the key yield-related factors in nowadays design. Routing is a suitable stage to reduce effect of random defects because it arranges interconnect to proper locations whereas the interconnects are the place likely to have failures happen. This work proposed a routing flow including global routing and track routing with random defect awareness. This work aims to solve the track routing problem while minimizing the cost function which includes the probability of failure. Experimental shows proposed routing flow has a faster runtime and reduces 10% of number of failure at most in Monte Carlo simulation method compared with previous work TROY.