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dc.contributor.authorHsu, Hsin-Wuen_US
dc.contributor.authorChen, Meng-Lingen_US
dc.contributor.authorChen, Hung-Mingen_US
dc.contributor.authorLi, Hung-Chunen_US
dc.contributor.authorChen, Shi-Haoen_US
dc.date.accessioned2018-08-21T05:56:55Z-
dc.date.available2018-08-21T05:56:55Z-
dc.date.issued2012-01-01en_US
dc.identifier.issn1530-1591en_US
dc.identifier.urihttp://hdl.handle.net/11536/146838-
dc.description.abstractDue to the advantage of flip-chip design in power distribution but controversial peripheral 10 placement in lower design cost, redistribution layer (RDL) is usually used for such interconnection. Sometimes RDL is so congested that the capacity for routing is insufficient. Routing therefore cannot be completed within a single layer even for manual routing. Although [2] proposed a routing algorithm that uses two layers of RDLs, but in practice the required routing area is a little more than one layer. We overcome this problem by adopting the concept of pseudo single-layer. With the heuristics for routing on mapped channels and observations on staggered pins to relieve vertical constraints, the area of 2-layer routing can be minimized and the routability is 100%. Comparisons of routing results between manual design, the commercial tool, and the proposed method are presented. We have shown the effectiveness on a real industrial case: it originally required fully manual design, the proposed method can finish RDL routing automatically and effectively.en_US
dc.language.isoen_USen_US
dc.titleOn Effective Flip-Chip Routing via Pseudo Single Redistribution Layeren_US
dc.typeProceedings Paperen_US
dc.identifier.journalDESIGN, AUTOMATION & TEST IN EUROPE (DATE 2012)en_US
dc.citation.spage1597en_US
dc.citation.epage1602en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000415126300302en_US
Appears in Collections:Conferences Paper