考量可繞線度之晶片封裝共同設計下的界面凸塊規劃

Abstract

在現今積體電路的晶片與封裝設計流程中，要同時在晶片、封裝、以及電路板三個領域達到界面凸塊規劃與界面凸塊繞線的最佳化是一件非常困難的事情。通常，整個設計流程需要大量的人力資源，除此之外，為了達到最佳化，工程師必須反覆重新規劃界面凸塊與繞線，因而降低了產品獲利。基於上述原因，我們針對晶片與封裝共同設計提出一個快速的啟發式演算法，以實現自動化界面凸塊規劃的目標，而且，藉由此演算法所規劃的界面凸塊將能使晶片重分配層與封裝繞線層具備很高的可繞線度(在我們的實際測試案件中達到了百分之百的可繞線度)。實驗結果顯示，本論文中提出的演算法(由逃脫繞線演算法所啟發)可在很短的時間內完成界面凸塊規劃、晶片重分配層繞線、以及封裝繞線；然而，傳統的晶片與封裝共同設計流程卻要花費數個禮拜甚至好幾個月才能實現整個設計。

In current chip and package designs, it is a bottleneck to simultaneously optimize both pin assignment and pin routing for different design domains (chip, package, and board). Usually, the whole process costs a huge manual effort and multiple iterations thus reducing profit margin. Therefore, we propose a fast heuristic chip-package co-design algorithm in order to automatically obtain a bump assignment which introduces high routability both in RDL routing and substrate routing (100\% in our real case). Experimental results show that the proposed method (inspired by board escape routing algorithms) automatically finishes bump assignment, RDL routing and substrate routing in a short time, while the traditional co-design flow requires weeks even months.