Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Chen, Hou-Yu | en_US |
dc.contributor.author | Chen, Chun-Chi | en_US |
dc.contributor.author | Hsueh, Fu-Kuo | en_US |
dc.contributor.author | Liu, Jan-Tsai | en_US |
dc.contributor.author | Shy, Shyi-Long | en_US |
dc.contributor.author | Wu, Cheng-San | en_US |
dc.contributor.author | Chien, Chao-Hsin | en_US |
dc.contributor.author | Hu, Chenming | en_US |
dc.contributor.author | Huang, Chien-Chao | en_US |
dc.contributor.author | Yang, Fu-Liang | en_US |
dc.date.accessioned | 2014-12-08T15:20:40Z | - |
dc.date.available | 2014-12-08T15:20:40Z | - |
dc.date.issued | 2011-11-01 | en_US |
dc.identifier.issn | 0018-9383 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/TED.2011.2163938 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/14690 | - |
dc.description.abstract | For more than 45 years, photon-and electron-sensitive materials have been used to produce pattern-transfer masks in the lithographic manufacturing of integrated circuits. With the semiconductor technology feature size continuing to shrink and the requirements of low-variability and low-cost manufacturing, optical lithography is driven to its limits. In this paper, we report a novel nanoinjection lithography (NInL) technique that employs electron-beam-assisted deposition to form pattern-transfer hard mask in a direct-write deposit approach. By scanning the 4.6-nm-diameter electron beam while injecting a suitable organometallic precursor gas around the location of e-beam and just above the substrate, we form a high-density (pitch: 40 nm) high-uniformity (3-sigma linewidth roughness: 2 nm) hard mask for subsequent etching without using proximity-effect correction techniques. Furthermore, this technique can also directly deposit a metal pattern for interconnect or a dielectric pattern without the need for separate metal or dielectric deposition, photoresist etch-mask, and etching processes. The NInL approach simplifies the hard-mask creation or even metal or dielectric pattern creation process modules from five or tens of steps to only a single step. Therefore, it saves both photomask making and wafer processing costs. In addition, room-temperature NInL deposition of conductor/dielectric materials enables the fabrication of small versatile devices and circuits. For demonstration, we fabricated a functional 16-nm six-transistor static random access memory (SRAM) cell (area: occupying only 0.039 mu m(2)), 43% the size of the smallest previously reported SRAM cell, using the FinFET structure and a dynamic V(dd) regulator approach. The NInL technique offers a new way of exploring low-volume high-value 16-nm complementary metal-oxide-semiconductor (CMOS) devices and circuit designs with minimal additional investment and obtains early access to extreme CMOS scaling. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | Direct-write | en_US |
dc.subject | electron beam (e-beam) | en_US |
dc.subject | FinFET | en_US |
dc.subject | nanoinjection lithography (NInL) | en_US |
dc.subject | static random access memory (SRAM) | en_US |
dc.title | A Novel Nanoinjection Lithography (NInL) Technology and Its Application for 16-nm Node Device Fabrication | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/TED.2011.2163938 | en_US |
dc.identifier.journal | IEEE TRANSACTIONS ON ELECTRON DEVICES | en_US |
dc.citation.volume | 58 | en_US |
dc.citation.issue | 11 | en_US |
dc.citation.spage | 3678 | en_US |
dc.citation.epage | 3686 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000296099400004 | - |
dc.citation.woscount | 1 | - |
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