Program/Erase Speed and Data Retention Trade-Off in Negative Capacitance Versatile Memory

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Fan, Chia-Chi	en_US
dc.contributor.author	Chiu, Yu-Chien	en_US
dc.contributor.author	Liu, Chien	en_US
dc.contributor.author	Liou, Guan-Lin	en_US
dc.contributor.author	Lai, Wen-Wei	en_US
dc.contributor.author	Chen, Yi-Ru	en_US
dc.contributor.author	Chang, Tun-Jen	en_US
dc.contributor.author	Chen, Wan-Hsin	en_US
dc.contributor.author	Cheng, Chun-Hu	en_US
dc.contributor.author	Chang, Chun-Yen	en_US
dc.date.accessioned	2018-08-21T05:57:00Z	-
dc.date.available	2018-08-21T05:57:00Z	-
dc.date.issued	2017-01-01	en_US
dc.identifier.issn	2161-4636	en_US
dc.identifier.uri	http://hdl.handle.net/11536/146935	-
dc.description.abstract	In this work, we investigated the performance tradeoff between program/erase speed and data retention of ferroelectric HfZrO memory. The monoclinic HfNO layer with a trapping mechanism was employed to improve the data retention. Under the thickness optimization of HfNO, the HfZrO/HfNO gate stack can be functionalized with volatile and non-volatile operation.	en_US
dc.language.iso	en_US	en_US
dc.title	Program/Erase Speed and Data Retention Trade-Off in Negative Capacitance Versatile Memory	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	2017 SILICON NANOELECTRONICS WORKSHOP (SNW)	en_US
dc.citation.spage	101	en_US
dc.citation.epage	102	en_US
dc.contributor.department	電子物理學系	zh_TW
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electrophysics	en_US
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000425209200051	en_US
顯示於類別：	會議論文