標題: Energy-Efficient Versatile Memories With Ferroelectric Negative Capacitance by Gate-Strain Enhancement
作者: Chiu, Yu-Chien
Cheng, Chun-Hu
Liou, Guan-Lin
Chang, Chun-Yen
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Charge trpapping;ferroelectric;multilevel;nonvolatile memory
公開日期: 1-八月-2017
摘要: In this brief, we reported a ferroelectric versatile memory with strained-gate engineering. The versatile memory with high-strain-gate showed a >40% improvement on ferroelectric hysteresis window, compared to low-strain case. The high compressive stress induced from high nitrogen-content TaN enhances monoclinic-to-orthorhombic phase transition to reach stronger ferrolectric polarization and lower depolarization field. The versatile memory featuring ferroelectric negative capacitance exhibited excellent transfer characteristics of the sub-60-mVdec subthreshold swing, ultralow off-state leakage of <1fA/mu m and > 108 on/off current ratio. Furthermore, the ferroelectric versatile memory can be switched by +/- 5 V under 20-ns speed for a long endurance cycling (similar to 10(12) cycles). The low-power operation can be ascribed to the amplification of the surface potential to reach the strong inversion and fast domain polarization at the correspondingly low program/erase voltages.
URI: http://dx.doi.org/10.1109/TED.2017.2712709
http://hdl.handle.net/11536/145832
ISSN: 0018-9383
DOI: 10.1109/TED.2017.2712709
期刊: IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume: 64
起始頁: 3498
結束頁: 3501
顯示於類別:期刊論文