標題: High Speed Negative Capacitance Ferroelectric Memory
作者: Chang, Chun-Yen
Fan, Chia-Chi
Liu, Chien
Chiu, Yu-Chien
Cheng, Chun-Hu
電子物理學系
電子工程學系及電子研究所
Department of Electrophysics
Department of Electronics Engineering and Institute of Electronics
公開日期: 1-一月-2017
摘要: This work experimentally demonstrated a one-transistor ferroelectric versatile memory with the multi-technique integration of negative-capacitance mechanism, ferroelectric polarization effect and metal-strained engineering. The negative-capacitance versatile memory featured a steep sub-60mV/dec subthreshold swing, fast 20-ns switching speed and long 1012 cycled endurance. We successfully demonstrated that the metal-gate-induced strain could help to improve ferroelectric phase transformation. The excellent endurance characteristics could be ascribed to efficient ferroelectric negative-capacitance switching under low program/erase voltages.
URI: http://hdl.handle.net/11536/147095
ISSN: 2162-7541
期刊: 2017 IEEE 12TH INTERNATIONAL CONFERENCE ON ASIC (ASICON)
起始頁: 1
結束頁: 5
顯示於類別:會議論文